common: Use NPNR_ASSERT_FALSE
for unreachable case
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parent
9c97b8736e
commit
3eeb0e2877
@ -30,7 +30,6 @@
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#include "archdefs.h"
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#include "archdefs.h"
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#include "hashlib.h"
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#include "hashlib.h"
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#include "indexed_store.h"
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#include "indexed_store.h"
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#include "log.h"
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#include "nextpnr_base_types.h"
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#include "nextpnr_base_types.h"
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#include "nextpnr_namespaces.h"
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#include "nextpnr_namespaces.h"
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#include "property.h"
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#include "property.h"
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@ -201,7 +200,7 @@ enum PortType
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case PORT_INOUT:
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case PORT_INOUT:
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return "PORT_INOUT";
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return "PORT_INOUT";
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default:
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default:
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log_error("Impossible PortType");
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NPNR_ASSERT_FALSE("Impossible PortType");
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}
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}
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}
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}
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@ -250,7 +249,7 @@ enum TimingPortClass
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case TMG_IGNORE:
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case TMG_IGNORE:
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return "TMG_IGNORE";
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return "TMG_IGNORE";
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default:
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default:
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log_error("Impossible TimingPortClass");
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NPNR_ASSERT_FALSE("Impossible TimingPortClass");
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}
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}
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}
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}
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@ -268,7 +267,7 @@ enum ClockEdge
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case FALLING_EDGE:
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case FALLING_EDGE:
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return "FALLING_EDGE";
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return "FALLING_EDGE";
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default:
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default:
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log_error("Impossible ClockEdge");
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NPNR_ASSERT_FALSE("Impossible ClockEdge");
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}
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}
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}
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}
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@ -438,7 +437,7 @@ struct CriticalPath
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case Type::HOLD:
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case Type::HOLD:
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return "hold";
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return "hold";
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default:
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default:
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log_error("Impossible Segment::Type");
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NPNR_ASSERT_FALSE("Impossible Segment::Type");
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}
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}
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}
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}
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@ -1318,7 +1318,7 @@ const std::string TimingAnalyser::arcType_to_str(CellArc::ArcType typ)
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case TimingAnalyser::CellArc::ENDPOINT:
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case TimingAnalyser::CellArc::ENDPOINT:
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return "ENDPOINT";
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return "ENDPOINT";
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default:
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default:
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log_error("Impossible CellArc::ArcType\n");
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NPNR_ASSERT_FALSE("Impossible CellArc::ArcType\n");
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}
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}
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}
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}
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