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DSP cascading

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This commit is contained in:
Miodrag Milanovic 2024-06-20 15:39:32 +02:00
parent db5d26c129
commit 3fa68b4a96
4 changed files with 46 additions and 2 deletions
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1
himbaechel/uarch/ng-ultra/extra_data.h
View File

@ -96,6 +96,7 @@ enum ClusterPlacement
PLACE_XRF_WA6,
PLACE_XRF_WE,
PLACE_XRF_WEA,
PLACE_DSP_CHAIN,
};
enum PipExtra

23
himbaechel/uarch/ng-ultra/ng_ultra.cc
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@ -86,6 +86,21 @@ void NgUltraImpl::init(Context *ctx)
}
locations.emplace(stringf("%s:%s",tile_name(bel.tile).c_str(), ctx->getBelName(bel)[1].c_str(ctx)),bel);
}
for (auto bel : ctx->getBels()) {
if (ctx->getBelType(bel) == id_DSP) {
WireId cco = ctx->getBelPinWire(bel,id_CCO);
WireId cci;
for (auto dh : ctx->getPipsDownhill(cco)) {
cci = ctx->getPipDstWire(dh);
}
if (cci!=WireId()) {
std::string loc = stringf("%s:%s",tile_name(cci.tile).c_str(), ctx->getWireName(cci)[1].c_str(ctx));
loc.erase(loc.find(".CCI"));
BelId dsp_bel = locations[loc];
dsp_cascade.emplace(dsp_bel, bel);
}
}
}
}
const NGUltraTileInstExtraDataPOD *NgUltraImpl::tile_extra_data(int tile) const
@ -421,6 +436,13 @@ bool NgUltraImpl::isValidBelForCellType(IdString cell_type, BelId bel) const
return (bel_type == cell_type);
}
Loc getNextLocInDSPChain(const NgUltraImpl *impl, Loc loc)
{
BelId bel = impl->ctx->getBelByLocation(loc);
BelId dsp = impl->dsp_cascade.at(bel);
return impl->ctx->getBelLocation(dsp);
}
Loc getNextLocInCYChain(Loc loc)
{
static const std::vector<Loc> map =
@ -567,6 +589,7 @@ bool NgUltraImpl::getChildPlacement(const BaseClusterInfo *cluster, Loc root_loc
case PLACE_CY_FE4: return getCYFE(root_loc,3);
case PLACE_XRF_I1 ... PLACE_XRF_WEA:
return getXRFFE(root_loc, child->constr_z - PLACE_XRF_I1 );
case PLACE_DSP_CHAIN : { Loc l = getNextLocInDSPChain(this, prev); prev = l; return l; }
default:
Loc result;
result.x = root_loc.x + child->constr_x;

1
himbaechel/uarch/ng-ultra/ng_ultra.h
View File

@ -77,6 +77,7 @@ public:
dict<IdString, std::pair<IdString,IdString>> bank_to_ckg;
dict<BelId, IdString> unused_wfg;
dict<BelId, IdString> unused_pll;
dict<BelId, BelId> dsp_cascade;
private:
void write_bitstream_json(const std::string &filename);

23
himbaechel/uarch/ng-ultra/pack.cc
View File

@ -1065,8 +1065,8 @@ void NgUltraPacker::insert_wfbs()
for (auto &cell : ctx->cells) {
CellInfo &ci = *cell.second;
if (ci.type.in(id_IOM)) {
//insert_wfb(&ci, id_CKO1);
//insert_wfb(&ci, id_CKO2);
insert_wfb(&ci, id_CKO1);
insert_wfb(&ci, id_CKO2);
} else if (ci.type.in(id_PLL)) {
insert_wfb(&ci, id_VCO);
insert_wfb(&ci, id_REFO);
@ -1349,6 +1349,8 @@ void NgUltraPacker::dsp_same_sink(IdString port, CellInfo *cell, CellInfo **targ
void NgUltraPacker::pack_dsps(void)
{
log_info("Packing DSPs..\n");
dict<IdString, CellInfo*> dsp_output;
std::vector<CellInfo *> root_dsps;
for (auto &cell : ctx->cells) {
CellInfo &ci = *cell.second;
if (!ci.type.in(id_NX_DSP_U))
@ -1370,6 +1372,8 @@ void NgUltraPacker::pack_dsps(void)
for(int i=1;i<=56;i++)
dsp_same_driver(ctx->idf("CZI%d",i), &ci, &dsp);
dsp_same_driver(id_CCI, &ci, &dsp);
if (!dsp)
root_dsps.push_back(&ci);
// CAO1-24, CBO1-18, CZO1..56 and CCO must go to same DSP
dsp = nullptr;
@ -1380,6 +1384,20 @@ void NgUltraPacker::pack_dsps(void)
for(int i=1;i<=56;i++)
dsp_same_sink(ctx->idf("CZO%d",i), &ci, &dsp);
dsp_same_sink(id_CCO, &ci, &dsp);
if (dsp)
dsp_output.emplace(ci.name, dsp);
}
for (auto root : root_dsps) {
CellInfo *dsp = root;
if (dsp_output.count(dsp->name)==0) continue;
root->cluster = root->name;
while (true) {
if (dsp_output.count(dsp->name)==0) break;
dsp = dsp_output[dsp->name];
dsp->cluster = root->name;
root->constr_children.push_back(dsp);
dsp->constr_z = PLACE_DSP_CHAIN;
}
}
}
void NgUltraPacker::setup()
@ -1698,6 +1716,7 @@ void NgUltraPacker::insert_bypass_gck()
clock_sinks[id_XPRF].insert(id_WCK2);
clock_sinks[id_RAM].insert(id_ACK);
clock_sinks[id_RAM].insert(id_BCK);
clock_sinks[id_DSP].insert(id_CK);
//glb_sources[id_BFR].insert(id_O);
//glb_sources[id_GCK].insert(id_SO);