Minor refactoring of router infrastructure
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
d5a032d00e
commit
3fda636e70
206
common/route.cc
206
common/route.cc
@ -61,111 +61,32 @@ void ripup_net(Context *ctx, IdString net_name)
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struct Router
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{
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Context *ctx;
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IdString net_name;
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bool ripup;
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delay_t ripup_penalty;
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std::unordered_set<IdString> rippedNets;
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std::unordered_map<WireId, QueuedWire> visited;
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int visitCnt = 0, revisitCnt = 0;
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bool routedOkay = false;
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delay_t maxDelay = 0.0;
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WireId failedDest;
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Router(Context *ctx, IdString net_name, bool ripup = false,
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delay_t ripup_penalty = 0)
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void route(const std::unordered_map<WireId, delay_t> &src_wires,
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WireId dst_wire)
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{
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auto net_info = ctx->nets.at(net_name);
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if (ctx->verbose)
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log("Routing net %s.\n", net_name.c_str(ctx));
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if (ctx->verbose)
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log(" Source: %s.%s.\n", net_info->driver.cell->name.c_str(ctx),
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net_info->driver.port.c_str(ctx));
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auto src_bel = net_info->driver.cell->bel;
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if (src_bel == BelId())
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log_error("Source cell %s (%s) is not mapped to a bel.\n",
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net_info->driver.cell->name.c_str(ctx),
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net_info->driver.cell->type.c_str(ctx));
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if (ctx->verbose)
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log(" Source bel: %s\n", ctx->getBelName(src_bel).c_str(ctx));
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IdString driver_port = net_info->driver.port;
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auto driver_port_it = net_info->driver.cell->pins.find(driver_port);
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if (driver_port_it != net_info->driver.cell->pins.end())
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driver_port = driver_port_it->second;
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auto src_wire =
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ctx->getWireBelPin(src_bel, ctx->portPinFromId(driver_port));
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if (src_wire == WireId())
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log_error("No wire found for port %s (pin %s) on source cell %s "
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"(bel %s).\n",
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net_info->driver.port.c_str(ctx), driver_port.c_str(ctx),
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net_info->driver.cell->name.c_str(ctx),
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ctx->getBelName(src_bel).c_str(ctx));
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if (ctx->verbose)
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log(" Source wire: %s\n", ctx->getWireName(src_wire).c_str(ctx));
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std::unordered_map<WireId, DelayInfo> src_wires;
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src_wires[src_wire] = DelayInfo();
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net_info->wires[src_wire] = PipId();
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ctx->bindWire(src_wire, net_name);
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std::vector<PortRef> users_array = net_info->users;
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ctx->shuffle(users_array);
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for (auto &user_it : users_array) {
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if (ctx->verbose)
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log(" Route to: %s.%s.\n", user_it.cell->name.c_str(ctx),
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user_it.port.c_str(ctx));
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auto dst_bel = user_it.cell->bel;
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if (dst_bel == BelId())
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log_error("Destination cell %s (%s) is not mapped to a bel.\n",
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user_it.cell->name.c_str(ctx),
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user_it.cell->type.c_str(ctx));
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if (ctx->verbose)
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log(" Destination bel: %s\n",
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ctx->getBelName(dst_bel).c_str(ctx));
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IdString user_port = user_it.port;
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auto user_port_it = user_it.cell->pins.find(user_port);
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if (user_port_it != user_it.cell->pins.end())
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user_port = user_port_it->second;
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auto dst_wire =
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ctx->getWireBelPin(dst_bel, ctx->portPinFromId(user_port));
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if (dst_wire == WireId())
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log_error("No wire found for port %s (pin %s) on destination "
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"cell %s (bel %s).\n",
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user_it.port.c_str(ctx), user_port.c_str(ctx),
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user_it.cell->name.c_str(ctx),
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ctx->getBelName(dst_bel).c_str(ctx));
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if (ctx->verbose) {
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log(" Destination wire: %s\n",
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ctx->getWireName(dst_wire).c_str(ctx));
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log(" Path delay estimate: %.2f\n",
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float(ctx->estimateDelay(src_wire, dst_wire)));
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}
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std::unordered_map<WireId, QueuedWire> visited;
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std::priority_queue<QueuedWire, std::vector<QueuedWire>,
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QueuedWire::Greater>
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queue;
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visited.clear();
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for (auto &it : src_wires) {
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QueuedWire qw;
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qw.wire = it.first;
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qw.pip = PipId();
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qw.delay = it.second.avgDelay();
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qw.delay = it.second;
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qw.togo = ctx->estimateDelay(qw.wire, dst_wire);
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qw.randtag = ctx->rng();
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@ -231,6 +152,109 @@ struct Router
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queue.push(next_qw);
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}
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}
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}
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Router(Context *ctx, WireId src_wire, WireId dst_wire, bool ripup = false,
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delay_t ripup_penalty = 0)
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: ctx(ctx), ripup(ripup), ripup_penalty(ripup_penalty)
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{
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std::unordered_map<WireId, delay_t> src_wires;
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src_wires[src_wire] = 0;
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route(src_wires, dst_wire);
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}
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Router(Context *ctx, IdString net_name, bool ripup = false,
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delay_t ripup_penalty = 0)
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: ctx(ctx), net_name(net_name), ripup(ripup),
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ripup_penalty(ripup_penalty)
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{
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auto net_info = ctx->nets.at(net_name);
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if (ctx->verbose)
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log("Routing net %s.\n", net_name.c_str(ctx));
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if (ctx->verbose)
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log(" Source: %s.%s.\n", net_info->driver.cell->name.c_str(ctx),
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net_info->driver.port.c_str(ctx));
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auto src_bel = net_info->driver.cell->bel;
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if (src_bel == BelId())
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log_error("Source cell %s (%s) is not mapped to a bel.\n",
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net_info->driver.cell->name.c_str(ctx),
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net_info->driver.cell->type.c_str(ctx));
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if (ctx->verbose)
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log(" Source bel: %s\n", ctx->getBelName(src_bel).c_str(ctx));
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IdString driver_port = net_info->driver.port;
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auto driver_port_it = net_info->driver.cell->pins.find(driver_port);
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if (driver_port_it != net_info->driver.cell->pins.end())
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driver_port = driver_port_it->second;
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auto src_wire =
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ctx->getWireBelPin(src_bel, ctx->portPinFromId(driver_port));
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if (src_wire == WireId())
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log_error("No wire found for port %s (pin %s) on source cell %s "
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"(bel %s).\n",
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net_info->driver.port.c_str(ctx), driver_port.c_str(ctx),
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net_info->driver.cell->name.c_str(ctx),
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ctx->getBelName(src_bel).c_str(ctx));
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if (ctx->verbose)
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log(" Source wire: %s\n", ctx->getWireName(src_wire).c_str(ctx));
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std::unordered_map<WireId, delay_t> src_wires;
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src_wires[src_wire] = 0;
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net_info->wires[src_wire] = PipId();
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ctx->bindWire(src_wire, net_name);
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std::vector<PortRef> users_array = net_info->users;
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ctx->shuffle(users_array);
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for (auto &user_it : users_array) {
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if (ctx->verbose)
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log(" Route to: %s.%s.\n", user_it.cell->name.c_str(ctx),
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user_it.port.c_str(ctx));
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auto dst_bel = user_it.cell->bel;
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if (dst_bel == BelId())
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log_error("Destination cell %s (%s) is not mapped to a bel.\n",
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user_it.cell->name.c_str(ctx),
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user_it.cell->type.c_str(ctx));
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if (ctx->verbose)
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log(" Destination bel: %s\n",
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ctx->getBelName(dst_bel).c_str(ctx));
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IdString user_port = user_it.port;
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auto user_port_it = user_it.cell->pins.find(user_port);
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if (user_port_it != user_it.cell->pins.end())
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user_port = user_port_it->second;
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auto dst_wire =
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ctx->getWireBelPin(dst_bel, ctx->portPinFromId(user_port));
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if (dst_wire == WireId())
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log_error("No wire found for port %s (pin %s) on destination "
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"cell %s (bel %s).\n",
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user_it.port.c_str(ctx), user_port.c_str(ctx),
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user_it.cell->name.c_str(ctx),
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ctx->getBelName(dst_bel).c_str(ctx));
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if (ctx->verbose) {
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log(" Destination wire: %s\n",
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ctx->getWireName(dst_wire).c_str(ctx));
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log(" Path delay estimate: %.2f\n",
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float(ctx->estimateDelay(src_wire, dst_wire)));
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}
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route(src_wires, dst_wire);
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if (visited.count(dst_wire) == 0) {
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if (ctx->verbose)
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@ -287,7 +311,7 @@ struct Router
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ctx->bindWire(cursor, net_name);
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ctx->bindPip(visited[cursor].pip, net_name);
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src_wires[cursor] = ctx->getPipDelay(visited[cursor].pip);
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src_wires[cursor] = visited[cursor].delay;
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cursor = ctx->getPipSrcWire(visited[cursor].pip);
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}
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}
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