Merge pull request #1031 from YosysHQ/gatecat/fab-next
fabulous: Add support for the CLB muxes
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commit
41709dac8f
@ -14,6 +14,7 @@ X(OutPass4_frame_config)
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X(RegFile_32x4)
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X(MULADD)
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X(MUX8LUT_frame_config)
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X(MUX8LUT_frame_config_mux)
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X(CLK)
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X(I)
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@ -86,3 +87,12 @@ X(BelBegin)
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X(BelEnd)
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X(GlobalClk)
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X(CFG)
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X(FABULOUS_MUX2)
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X(FABULOUS_MUX4)
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X(FABULOUS_MUX8)
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X(M_AB)
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X(M_AD)
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X(M_EF)
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X(M_AH)
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@ -293,12 +293,49 @@ struct FabulousImpl : ViaductAPI
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postprocess_bels();
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}
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void generate_split_mux8(BelId bel)
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{
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// _don't_ take a reference here because it might be invalidated by adding bels
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auto data = ctx->bel_info(bel);
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const std::array<IdString, 4> mux_outs{id_M_AB, id_M_AD, id_M_EF, id_M_AH};
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for (unsigned k = 1; k <= 3; k++) {
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// create MUX2 through 8
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unsigned m = (1U << k);
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for (unsigned i = 0; i < 8; i += m) {
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// mux indexing scheme
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// - MUX2s are at (z % 2) == 0
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// - MUX4s are at (z % 4) == 1
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// - MUX8s are at (z % 8) == 7
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int idx = (m == 2) ? i : (m == 4) ? (i + 1) : (i + 7);
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BelId mux =
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ctx->addBel(IdStringList::concat(data.name[0], ctx->idf("MUX%d_%d", m, i)),
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ctx->idf("FABULOUS_MUX%d", m), Loc(data.x, data.y, data.z + 1 + idx), false, false);
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blk_trk->set_bel_type(mux, BelFlags::BLOCK_CLB, BelFlags::FUNC_MUX, idx);
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// M data inputs
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for (unsigned j = 0; j < m; j++) {
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ctx->addBelInput(mux, ctx->idf("I%d", j), data.pins.at(ctx->idf("%c", char('A' + i + j))).wire);
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}
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// K select inputs
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for (unsigned j = 0; j < k; j++) {
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ctx->addBelInput(mux, ctx->idf("S%d", j),
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data.pins.at(ctx->idf("S%d", (m == 8 && j == 2) ? 3 : ((i / m) * k + j))).wire);
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}
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// Output
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IdString output = (m == 2) ? mux_outs.at(i / m)
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: (m == 4) ? mux_outs.at((i / m) * k + 1)
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: mux_outs.at(3);
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ctx->addBelOutput(mux, id_O, data.pins.at(output).wire);
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}
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}
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}
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void postprocess_bels()
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{
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// This does some post-processing on bels to make them useful for nextpnr place-and-route regardless of the code
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// path that creates them. In the future, splitting muxes and creating split LCs would be done here, too
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for (auto bel : ctx->getBels()) {
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auto &data = ctx->bel_info(bel);
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// _don't_ take a reference here because it might be invalidated by adding bels
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auto data = ctx->bel_info(bel);
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if (data.type == id_FABULOUS_LC) {
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if (!data.pins.count(id_Q)) {
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// Add a Q pseudo-pin and pseudo-pip from Q to O
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@ -309,6 +346,9 @@ struct FabulousImpl : ViaductAPI
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// Pseudo-pip for FF mode
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add_pseudo_pip(q_wire, o_wire, id_O2Q);
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}
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} else if (data.type.in(id_MUX8LUT_frame_config, id_MUX8LUT_frame_config_mux)) {
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generate_split_mux8(bel);
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ctx->bel_info(bel).hidden = true;
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} else if (data.type == id_IO_1_bidirectional_frame_config_pass) {
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if (!data.pins.count(id_PAD)) {
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// Add a PAD pseudo-pin for the top level
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@ -123,6 +123,14 @@ struct FabFasmWriter
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write_bool(lc, "NEG_SR");
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write_bool(lc, "ASYNC_SR");
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}
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if (lc->type.in(id_FABULOUS_MUX4, id_FABULOUS_MUX8)) {
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// TODO: don't hardcode prefix
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out << prefix << "I.c0" << std::endl;
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}
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if (lc->type == id_FABULOUS_MUX8) {
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// TODO: don't hardcode prefix
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out << prefix << "I.c1" << std::endl;
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}
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}
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void write_io(const CellInfo *io)
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@ -161,7 +169,8 @@ struct FabFasmWriter
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void write_cell(const CellInfo *ci)
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{
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out << stringf("# config for cell '%s'\n", ctx->nameOf(ci)) << std::endl;
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if (ci->type.in(id_FABULOUS_COMB, id_FABULOUS_FF, id_FABULOUS_LC))
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if (ci->type.in(id_FABULOUS_COMB, id_FABULOUS_FF, id_FABULOUS_LC, id_FABULOUS_MUX2, id_FABULOUS_MUX4,
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id_FABULOUS_MUX8))
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write_logic(ci);
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else if (ci->type == id_IO_1_bidirectional_frame_config_pass)
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write_io(ci);
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@ -132,6 +132,53 @@ struct FabulousPacker
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}
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}
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void pack_muxes()
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{
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// TODO: don't hardcode z-offset -- we should come up with our own constraint structure
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int lut_muxes_dz = 9;
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int lut_lut_dz = 1;
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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unsigned k = 0;
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if (ci->type == id_FABULOUS_MUX2)
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k = 1;
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else if (ci->type == id_FABULOUS_MUX4)
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k = 2;
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else if (ci->type == id_FABULOUS_MUX8)
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k = 3;
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else
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continue;
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unsigned m = (1U << k);
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std::vector<CellInfo *> luts;
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for (unsigned i = 0; i < m; i++) {
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NetInfo *ii = ci->getPort(ctx->idf("I%d", i));
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if (!ii || !ii->driver.cell || !ii->driver.cell->type.in(id_FABULOUS_LC, id_FABULOUS_COMB) ||
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ii->driver.port != id_O)
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log_error("mux %s input I%d net %s is not driven by a LUT!\n", ctx->nameOf(ci), i, ctx->nameOf(ii));
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CellInfo *lut = ii->driver.cell;
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NPNR_ASSERT(lut->cluster == ClusterId());
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luts.push_back(lut);
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}
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luts.at(0)->cluster = luts.at(0)->name;
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for (unsigned i = 0; i < m; i++) {
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luts.at(i)->cluster = luts.at(0)->name;
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luts.at(i)->constr_x = 0;
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luts.at(i)->constr_y = 0;
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luts.at(i)->constr_z = i * lut_lut_dz;
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luts.at(i)->constr_abs_z = false;
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if (i > 0)
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luts.at(0)->constr_children.push_back(luts.at(i));
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}
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int extra_mux_dz = (m == 8) ? 7 : (m == 4) ? 1 : 0;
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ci->cluster = luts.at(0)->name;
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ci->constr_x = 0;
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ci->constr_y = 0;
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ci->constr_z = lut_muxes_dz + extra_mux_dz;
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ci->constr_abs_z = false;
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luts.at(0)->constr_children.push_back(ci);
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}
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}
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void pack_ffs()
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{
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pool<IdString> to_delete;
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@ -238,6 +285,7 @@ struct FabulousPacker
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handle_constants();
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handle_io();
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pack_luts();
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pack_muxes();
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prepare_ffs();
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pack_ffs();
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}
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@ -33,6 +33,7 @@ CLBState::CLBState(const LogicConfig &cfg)
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if (cfg.split_lc) {
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ff = std::make_unique<CellInfo *[]>(cfg.lc_per_clb * cfg.ff_per_lc);
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}
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mux = std::make_unique<CellInfo *[]>(cfg.lc_per_clb);
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// TODO: mux
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}
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@ -173,6 +174,26 @@ bool CLBState::check_validity(const LogicConfig &cfg, const CellTagger &cell_dat
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}
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}
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}
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// don't allow mixed MUX types in the classic fabulous arch where ctrl sigs are shared
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int tile_mux_type = 0;
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for (unsigned z = 0; z < cfg.lc_per_clb; z++) {
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const CellInfo *m = mux[z];
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if (!m)
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continue;
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int this_mux = 0;
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if (m->type == id_FABULOUS_MUX2)
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this_mux = 2;
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else if (m->type == id_FABULOUS_MUX4)
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this_mux = 4;
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else if (m->type == id_FABULOUS_MUX8)
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this_mux = 8;
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else
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NPNR_ASSERT_FALSE("unknown mux type");
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if (tile_mux_type == 0)
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tile_mux_type = this_mux;
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else if (tile_mux_type != this_mux)
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return false;
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}
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// TODO: other checks...
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return true;
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}
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