caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

ecp5: Architecture fixes

Browse Source 
Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-07-08 13:29:13 +02:00
parent 49f39b8d56
commit 417913fd85
2 changed files with 5 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
ecp5/arch.h
View File

@ -672,7 +672,9 @@ struct Arch : BaseCtx
PipRange range;
NPNR_ASSERT(wire != WireId());
range.b.cursor = locInfo(wire)->wire_data[wire.index].pips_downhill.get();
range.b.wire_loc = wire.location;
range.e.cursor = range.b.cursor + locInfo(wire)->wire_data[wire.index].num_downhill;
range.e.wire_loc = wire.location;
return range;
}
@ -681,7 +683,9 @@ struct Arch : BaseCtx
PipRange range;
NPNR_ASSERT(wire != WireId());
range.b.cursor = locInfo(wire)->wire_data[wire.index].pips_uphill.get();
range.b.wire_loc = wire.location;
range.e.cursor = range.b.cursor + locInfo(wire)->wire_data[wire.index].num_uphill;
range.e.wire_loc = wire.location;
return range;
}

2
ecp5/trellis_import.py
View File

@ -297,7 +297,7 @@ class BinaryBlobAssembler:
assert len(self.data) % 2 == 0
if self.nodebug:
comment = None
c2val = (~v + 1) if v < 0 else v
c2val = (((-v) ^ 0xffff) + 1) if v < 0 else v
if self.endianness == "le":
self.data.append(c2val & 255)
self.data.append((c2val >> 8) & 255)