From 442142a47afd4005f15832bf40d35d3b2e6063d1 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 30 Mar 2023 13:17:37 +0200 Subject: [PATCH] typo fixes --- machxo2/arch.cc | 2 +- machxo2/bitstream.cc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/machxo2/arch.cc b/machxo2/arch.cc index 32b188e6..5b6f6cae 100644 --- a/machxo2/arch.cc +++ b/machxo2/arch.cc @@ -101,7 +101,7 @@ Arch::Arch(ArchArgs args) : args(args) auto &tile_data = chip_info->tile_info[i]; ts.boundcells.resize(chip_info->tiles[i].bel_data.size(), nullptr); for (auto &name : tile_data.tile_names) { - if (strcmp(chip_info->tiletype_names[name.type_idx].get(), "PLC2") == 0) { + if (strcmp(chip_info->tiletype_names[name.type_idx].get(), "PLC") == 0) { // Is a logic tile ts.lts = new LogicTileStatus(); break; diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc index b2297be6..57eb87da 100644 --- a/machxo2/bitstream.cc +++ b/machxo2/bitstream.cc @@ -571,7 +571,7 @@ void write_bitstream(Context *ctx, std::string text_config_file) cc.tiles[tname].add_enum("CLK1.CLKMUX", str_or_default(ci->params, id_CLKMUX, "0")); } } else if (ci->type == id_TRELLIS_RAMW) { - std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC2"); + std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC"); cc.tiles[tname].add_enum("SLICEC.MODE", "RAMW"); cc.tiles[tname].add_word("SLICEC.K0.INIT", std::vector(16, false)); cc.tiles[tname].add_word("SLICEC.K1.INIT", std::vector(16, false));