caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

typo fixes

Browse Source
This commit is contained in:
Miodrag Milanovic 2023-03-30 13:17:37 +02:00 committed by myrtle
parent 398b2ab569
commit 442142a47a
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
machxo2/arch.cc
View File

@ -101,7 +101,7 @@ Arch::Arch(ArchArgs args) : args(args)
auto &tile_data = chip_info->tile_info[i]; auto &tile_data = chip_info->tile_info[i];
ts.boundcells.resize(chip_info->tiles[i].bel_data.size(), nullptr); ts.boundcells.resize(chip_info->tiles[i].bel_data.size(), nullptr);
for (auto &name : tile_data.tile_names) { for (auto &name : tile_data.tile_names) {
if (strcmp(chip_info->tiletype_names[name.type_idx].get(), "PLC2") == 0) { if (strcmp(chip_info->tiletype_names[name.type_idx].get(), "PLC") == 0) {
// Is a logic tile // Is a logic tile
ts.lts = new LogicTileStatus(); ts.lts = new LogicTileStatus();
break; break;

2
machxo2/bitstream.cc
View File

@ -571,7 +571,7 @@ void write_bitstream(Context *ctx, std::string text_config_file)
cc.tiles[tname].add_enum("CLK1.CLKMUX", str_or_default(ci->params, id_CLKMUX, "0")); cc.tiles[tname].add_enum("CLK1.CLKMUX", str_or_default(ci->params, id_CLKMUX, "0"));
} }
} else if (ci->type == id_TRELLIS_RAMW) { } else if (ci->type == id_TRELLIS_RAMW) {
std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC2"); std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC");
cc.tiles[tname].add_enum("SLICEC.MODE", "RAMW"); cc.tiles[tname].add_enum("SLICEC.MODE", "RAMW");
cc.tiles[tname].add_word("SLICEC.K0.INIT", std::vector<bool>(16, false)); cc.tiles[tname].add_word("SLICEC.K0.INIT", std::vector<bool>(16, false));
cc.tiles[tname].add_word("SLICEC.K1.INIT", std::vector<bool>(16, false)); cc.tiles[tname].add_word("SLICEC.K1.INIT", std::vector<bool>(16, false));