caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

nexus: Add global networks

Browse Source 
Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2020-01-12 20:44:22 +00:00
parent 140baf7037
commit 44f98c545b
4 changed files with 13 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
common/nextpnr.cc
View File

@ -506,7 +506,7 @@ void Context::check() const
}
}
}
#ifdef CHECK_WIRES
for (auto w : getWires()) {
auto ni = getBoundWireNet(w);
if (ni != nullptr) {
@ -514,7 +514,7 @@ void Context::check() const
CHECK_FAIL("wire '%s' missing in wires map of bound net '%s'\n", nameOfWire(w), nameOf(ni));
}
}
#endif
for (auto &c : cells) {
auto ci = c.second.get();
if (c.first != ci->name)

3
nexus/arch.cc
View File

@ -382,6 +382,9 @@ bool Arch::place()
if (placer == "heap") {
PlacerHeapCfg cfg(getCtx());
cfg.ioBufTypes.insert(id_SEIO33_CORE);
cfg.ioBufTypes.insert(id_SEIO18_CORE);
cfg.ioBufTypes.insert(id_OSC_CORE);
cfg.criticalityExponent = 7;
if (!placer_heap(getCtx(), cfg))
return false;

5
nexus/arch.h
View File

@ -362,7 +362,7 @@ inline bool chip_branch_tile(const ChipInfoPOD *chip, int32_t x, int32_t y, int3
int32_t branch_x;
if (!chip_get_branch_loc(chip, x, branch_x))
return false;
next = chip_tile_from_xy(chip, x, y);
next = chip_tile_from_xy(chip, branch_x, y);
return true;
}
inline bool chip_rel_loc_tile(const ChipInfoPOD *chip, int32_t base, const RelWireInfoPOD &rel, int32_t &next)
@ -1258,7 +1258,8 @@ struct Arch : BaseCtx
}
inline WireId canonical_wire(int32_t tile, uint16_t index) const
{
return chip_canonical_wire(db, chip_info, tile, index);
WireId c = chip_canonical_wire(db, chip_info, tile, index);
return c;
}
IdString pip_src_wire_name(PipId pip) const
{

5
nexus/constids.inc
View File

@ -103,3 +103,8 @@ X(CIB_T)
X(CIB_LR)
X(IO_TYPE)
X(OSC_CORE)
X(HFCLKOUT)
X(LFCLKOUT)