Improve iCE40 gfx for IO tiles and RAM tiles
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
5500cf3aff
commit
456a83430a
@ -342,15 +342,19 @@ std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) co
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std::vector<std::pair<IdString, std::string>> ret;
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auto &wi = chip_info->wire_data[wire.index];
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ret.push_back(std::make_pair(id("INDEX"), stringf("%d", wi.netidx)));
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ret.push_back(std::make_pair(id("GRID_X"), stringf("%d", wi.x)));
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ret.push_back(std::make_pair(id("GRID_Y"), stringf("%d", wi.y)));
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ret.push_back(std::make_pair(id("GRID_Z"), stringf("%d", wi.z)));
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#if 0
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for (int i = 0; i < wi.num_segments; i++) {
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auto &si = wi.segments[i];
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ret.push_back(std::make_pair(id(stringf("segment[%d]", i)),
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stringf("X%d/Y%d/%s", si.x, si.y, chip_info->tile_wire_names[si.index].get())));
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}
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#endif
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return ret;
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}
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@ -760,7 +764,7 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
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GraphicElement el;
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el.type = GraphicElement::TYPE_BOX;
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el.style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
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el.x1 = chip_info->bel_data[bel.index].x + logic_cell_x1;
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el.x1 = chip_info->bel_data[bel.index].x + lut_swbox_x1;
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el.x2 = chip_info->bel_data[bel.index].x + logic_cell_x2;
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el.y1 = chip_info->bel_data[bel.index].y + logic_cell_y1 +
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(4 * chip_info->bel_data[bel.index].z) * logic_cell_pitch;
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@ -774,7 +778,7 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
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GraphicElement el;
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el.type = GraphicElement::TYPE_BOX;
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el.style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
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el.x1 = chip_info->bel_data[bel.index].x + logic_cell_x1;
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el.x1 = chip_info->bel_data[bel.index].x + lut_swbox_x1;
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el.x2 = chip_info->bel_data[bel.index].x + logic_cell_x2;
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el.y1 = chip_info->bel_data[bel.index].y + logic_cell_y1 + i;
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el.y2 = chip_info->bel_data[bel.index].y + logic_cell_y2 + i + 7 * logic_cell_pitch;
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@ -108,6 +108,8 @@ NPNR_PACKED_STRUCT(struct WireInfoPOD {
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};
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RelPtr<char> name;
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int32_t netidx;
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int32_t num_uphill, num_downhill;
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RelPtr<int32_t> pips_uphill, pips_downhill;
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200
ice40/chipdb.py
200
ice40/chipdb.py
@ -96,6 +96,128 @@ with open(args.gfxh) as f:
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gfx_wire_ids[name] = idx
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gfx_wire_names.append(name)
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def gfx_wire_alias(old, new):
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assert old in gfx_wire_ids
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assert new not in gfx_wire_ids
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gfx_wire_ids[new] = gfx_wire_ids[old]
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# GFX aliases for RAM tiles
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gfx_wire_alias("TILE_WIRE_LUTFF_0_IN_0", "TILE_WIRE_RAM_RADDR_0")
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gfx_wire_alias("TILE_WIRE_LUTFF_0_IN_1", "TILE_WIRE_RAM_RADDR_1")
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gfx_wire_alias("TILE_WIRE_LUTFF_0_IN_2", "TILE_WIRE_RAM_RADDR_2")
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gfx_wire_alias("TILE_WIRE_LUTFF_0_IN_3", "TILE_WIRE_RAM_RADDR_3")
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gfx_wire_alias("TILE_WIRE_LUTFF_1_IN_0", "TILE_WIRE_RAM_RADDR_4")
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gfx_wire_alias("TILE_WIRE_LUTFF_1_IN_1", "TILE_WIRE_RAM_RADDR_5")
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gfx_wire_alias("TILE_WIRE_LUTFF_1_IN_2", "TILE_WIRE_RAM_RADDR_6")
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gfx_wire_alias("TILE_WIRE_LUTFF_1_IN_3", "TILE_WIRE_RAM_RADDR_7")
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gfx_wire_alias("TILE_WIRE_LUTFF_2_IN_0", "TILE_WIRE_RAM_RADDR_8")
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gfx_wire_alias("TILE_WIRE_LUTFF_2_IN_1", "TILE_WIRE_RAM_RADDR_9")
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gfx_wire_alias("TILE_WIRE_LUTFF_2_IN_2", "TILE_WIRE_RAM_RADDR_10")
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gfx_wire_alias("TILE_WIRE_LUTFF_0_IN_0", "TILE_WIRE_RAM_WADDR_0")
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gfx_wire_alias("TILE_WIRE_LUTFF_0_IN_1", "TILE_WIRE_RAM_WADDR_1")
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gfx_wire_alias("TILE_WIRE_LUTFF_0_IN_2", "TILE_WIRE_RAM_WADDR_2")
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gfx_wire_alias("TILE_WIRE_LUTFF_0_IN_3", "TILE_WIRE_RAM_WADDR_3")
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gfx_wire_alias("TILE_WIRE_LUTFF_1_IN_0", "TILE_WIRE_RAM_WADDR_4")
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gfx_wire_alias("TILE_WIRE_LUTFF_1_IN_1", "TILE_WIRE_RAM_WADDR_5")
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gfx_wire_alias("TILE_WIRE_LUTFF_1_IN_2", "TILE_WIRE_RAM_WADDR_6")
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gfx_wire_alias("TILE_WIRE_LUTFF_1_IN_3", "TILE_WIRE_RAM_WADDR_7")
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gfx_wire_alias("TILE_WIRE_LUTFF_2_IN_0", "TILE_WIRE_RAM_WADDR_8")
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gfx_wire_alias("TILE_WIRE_LUTFF_2_IN_1", "TILE_WIRE_RAM_WADDR_9")
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gfx_wire_alias("TILE_WIRE_LUTFF_2_IN_2", "TILE_WIRE_RAM_WADDR_10")
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gfx_wire_alias("TILE_WIRE_LUTFF_3_IN_0", "TILE_WIRE_RAM_MASK_0")
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gfx_wire_alias("TILE_WIRE_LUTFF_3_IN_1", "TILE_WIRE_RAM_MASK_1")
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gfx_wire_alias("TILE_WIRE_LUTFF_3_IN_2", "TILE_WIRE_RAM_MASK_2")
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gfx_wire_alias("TILE_WIRE_LUTFF_3_IN_3", "TILE_WIRE_RAM_MASK_3")
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gfx_wire_alias("TILE_WIRE_LUTFF_4_IN_0", "TILE_WIRE_RAM_MASK_4")
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gfx_wire_alias("TILE_WIRE_LUTFF_4_IN_1", "TILE_WIRE_RAM_MASK_5")
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gfx_wire_alias("TILE_WIRE_LUTFF_4_IN_2", "TILE_WIRE_RAM_MASK_6")
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gfx_wire_alias("TILE_WIRE_LUTFF_4_IN_3", "TILE_WIRE_RAM_MASK_7")
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gfx_wire_alias("TILE_WIRE_LUTFF_3_IN_0", "TILE_WIRE_RAM_MASK_8")
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gfx_wire_alias("TILE_WIRE_LUTFF_3_IN_1", "TILE_WIRE_RAM_MASK_9")
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gfx_wire_alias("TILE_WIRE_LUTFF_3_IN_2", "TILE_WIRE_RAM_MASK_10")
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gfx_wire_alias("TILE_WIRE_LUTFF_3_IN_3", "TILE_WIRE_RAM_MASK_11")
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gfx_wire_alias("TILE_WIRE_LUTFF_4_IN_0", "TILE_WIRE_RAM_MASK_12")
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gfx_wire_alias("TILE_WIRE_LUTFF_4_IN_1", "TILE_WIRE_RAM_MASK_13")
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gfx_wire_alias("TILE_WIRE_LUTFF_4_IN_2", "TILE_WIRE_RAM_MASK_14")
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gfx_wire_alias("TILE_WIRE_LUTFF_4_IN_3", "TILE_WIRE_RAM_MASK_15")
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gfx_wire_alias("TILE_WIRE_LUTFF_5_IN_0", "TILE_WIRE_RAM_WDATA_0")
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gfx_wire_alias("TILE_WIRE_LUTFF_5_IN_1", "TILE_WIRE_RAM_WDATA_1")
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gfx_wire_alias("TILE_WIRE_LUTFF_5_IN_2", "TILE_WIRE_RAM_WDATA_2")
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gfx_wire_alias("TILE_WIRE_LUTFF_5_IN_3", "TILE_WIRE_RAM_WDATA_3")
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gfx_wire_alias("TILE_WIRE_LUTFF_6_IN_0", "TILE_WIRE_RAM_WDATA_4")
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gfx_wire_alias("TILE_WIRE_LUTFF_6_IN_1", "TILE_WIRE_RAM_WDATA_5")
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gfx_wire_alias("TILE_WIRE_LUTFF_6_IN_2", "TILE_WIRE_RAM_WDATA_6")
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gfx_wire_alias("TILE_WIRE_LUTFF_6_IN_3", "TILE_WIRE_RAM_WDATA_7")
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gfx_wire_alias("TILE_WIRE_LUTFF_5_IN_0", "TILE_WIRE_RAM_WDATA_8")
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gfx_wire_alias("TILE_WIRE_LUTFF_5_IN_1", "TILE_WIRE_RAM_WDATA_9")
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gfx_wire_alias("TILE_WIRE_LUTFF_5_IN_2", "TILE_WIRE_RAM_WDATA_10")
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gfx_wire_alias("TILE_WIRE_LUTFF_5_IN_3", "TILE_WIRE_RAM_WDATA_11")
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gfx_wire_alias("TILE_WIRE_LUTFF_6_IN_0", "TILE_WIRE_RAM_WDATA_12")
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gfx_wire_alias("TILE_WIRE_LUTFF_6_IN_1", "TILE_WIRE_RAM_WDATA_13")
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gfx_wire_alias("TILE_WIRE_LUTFF_6_IN_2", "TILE_WIRE_RAM_WDATA_14")
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gfx_wire_alias("TILE_WIRE_LUTFF_6_IN_3", "TILE_WIRE_RAM_WDATA_15")
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gfx_wire_alias("TILE_WIRE_LUTFF_0_OUT", "TILE_WIRE_RAM_RDATA_0")
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gfx_wire_alias("TILE_WIRE_LUTFF_1_OUT", "TILE_WIRE_RAM_RDATA_1")
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gfx_wire_alias("TILE_WIRE_LUTFF_2_OUT", "TILE_WIRE_RAM_RDATA_2")
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gfx_wire_alias("TILE_WIRE_LUTFF_3_OUT", "TILE_WIRE_RAM_RDATA_3")
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gfx_wire_alias("TILE_WIRE_LUTFF_4_OUT", "TILE_WIRE_RAM_RDATA_4")
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gfx_wire_alias("TILE_WIRE_LUTFF_5_OUT", "TILE_WIRE_RAM_RDATA_5")
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gfx_wire_alias("TILE_WIRE_LUTFF_6_OUT", "TILE_WIRE_RAM_RDATA_6")
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gfx_wire_alias("TILE_WIRE_LUTFF_7_OUT", "TILE_WIRE_RAM_RDATA_7")
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gfx_wire_alias("TILE_WIRE_LUTFF_0_OUT", "TILE_WIRE_RAM_RDATA_8")
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gfx_wire_alias("TILE_WIRE_LUTFF_1_OUT", "TILE_WIRE_RAM_RDATA_9")
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gfx_wire_alias("TILE_WIRE_LUTFF_2_OUT", "TILE_WIRE_RAM_RDATA_10")
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gfx_wire_alias("TILE_WIRE_LUTFF_3_OUT", "TILE_WIRE_RAM_RDATA_11")
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gfx_wire_alias("TILE_WIRE_LUTFF_4_OUT", "TILE_WIRE_RAM_RDATA_12")
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gfx_wire_alias("TILE_WIRE_LUTFF_5_OUT", "TILE_WIRE_RAM_RDATA_13")
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gfx_wire_alias("TILE_WIRE_LUTFF_6_OUT", "TILE_WIRE_RAM_RDATA_14")
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gfx_wire_alias("TILE_WIRE_LUTFF_7_OUT", "TILE_WIRE_RAM_RDATA_15")
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gfx_wire_alias("TILE_WIRE_FUNC_GLOBAL_CEN", "TILE_WIRE_RAM_RCLKE")
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gfx_wire_alias("TILE_WIRE_FUNC_GLOBAL_CEN", "TILE_WIRE_RAM_WCLKE")
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gfx_wire_alias("TILE_WIRE_FUNC_GLOBAL_CLK", "TILE_WIRE_RAM_RCLK")
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gfx_wire_alias("TILE_WIRE_FUNC_GLOBAL_CLK", "TILE_WIRE_RAM_WCLK")
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gfx_wire_alias("TILE_WIRE_FUNC_GLOBAL_S_R", "TILE_WIRE_RAM_RE")
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gfx_wire_alias("TILE_WIRE_FUNC_GLOBAL_S_R", "TILE_WIRE_RAM_WE")
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# GFX aliases for IO tiles
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gfx_wire_alias("TILE_WIRE_LUTFF_0_IN_0", "TILE_WIRE_IO_0_D_OUT_0")
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gfx_wire_alias("TILE_WIRE_LUTFF_0_IN_1", "TILE_WIRE_IO_0_D_OUT_1")
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gfx_wire_alias("TILE_WIRE_LUTFF_0_IN_3", "TILE_WIRE_IO_0_OUT_ENB")
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gfx_wire_alias("TILE_WIRE_LUTFF_0_OUT", "TILE_WIRE_IO_0_D_IN_0")
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gfx_wire_alias("TILE_WIRE_LUTFF_1_OUT", "TILE_WIRE_IO_0_D_IN_1")
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gfx_wire_alias("TILE_WIRE_LUTFF_4_IN_0", "TILE_WIRE_IO_1_D_OUT_0")
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gfx_wire_alias("TILE_WIRE_LUTFF_4_IN_1", "TILE_WIRE_IO_1_D_OUT_1")
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gfx_wire_alias("TILE_WIRE_LUTFF_4_IN_3", "TILE_WIRE_IO_1_OUT_ENB")
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gfx_wire_alias("TILE_WIRE_LUTFF_4_OUT", "TILE_WIRE_IO_1_D_IN_0")
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gfx_wire_alias("TILE_WIRE_LUTFF_5_OUT", "TILE_WIRE_IO_1_D_IN_1")
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gfx_wire_alias("TILE_WIRE_FUNC_GLOBAL_CEN", "TILE_WIRE_IO_GLOBAL_CEN")
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gfx_wire_alias("TILE_WIRE_FUNC_GLOBAL_CLK", "TILE_WIRE_IO_GLOBAL_INCLK")
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gfx_wire_alias("TILE_WIRE_FUNC_GLOBAL_S_R", "TILE_WIRE_IO_GLOBAL_OUTCLK")
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gfx_wire_alias("TILE_WIRE_FUNC_GLOBAL_G0", "TILE_WIRE_IO_GLOBAL_LATCH")
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def read_timings(filename):
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db = dict()
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with open(filename) as f:
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@ -167,6 +289,18 @@ def maj_wire_name(name):
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return name[2] in ("sp12_v_b_0", "sp12_v_b_1")
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return False
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def norm_wire_xy(x, y, name):
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if name.startswith("glb_netwk_"):
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return None
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if name.startswith("neigh_op_"):
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return None
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if name.startswith("logic_op_"):
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return None
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if name.startswith("io_global/latch"):
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return None
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return None # FIXME
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return (x, y)
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def cmp_wire_names(newname, oldname):
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if maj_wire_name(newname):
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return True
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@ -510,11 +644,13 @@ with open(args.filename, "r") as f:
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wire_names_r[mode[1]] = wname
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if mode[1] not in wire_xy:
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wire_xy[mode[1]] = list()
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wire_xy[mode[1]].append((int(line[0]), int(line[1])))
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wire_xy[mode[1]].append(wname)
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if mode[1] not in wire_segments:
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wire_segments[mode[1]] = dict()
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if ("TILE_WIRE_" + wname[2].upper().replace("/", "_")) in gfx_wire_ids:
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wire_segments[mode[1]][(wname[0], wname[1])] = wname[2]
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if (wname[0], wname[1]) not in wire_segments[mode[1]]:
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wire_segments[mode[1]][(wname[0], wname[1])] = list()
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wire_segments[mode[1]][(wname[0], wname[1])].append(wname[2])
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continue
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if mode[0] in ("buffer", "routing"):
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@ -563,7 +699,9 @@ def add_wire(x, y, name):
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wire_names_r[wire_idx] = wname
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wire_segments[wire_idx] = dict()
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if ("TILE_WIRE_" + wname[2].upper().replace("/", "_")) in gfx_wire_ids:
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wire_segments[wire_idx][(wname[0], wname[1])] = wname[2]
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if (wname[0], wname[1]) not in wire_segments[wire_idx]:
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wire_segments[wire_idx][(wname[0], wname[1])] = list()
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wire_segments[wire_idx][(wname[0], wname[1])].append(wname[2])
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return wire_idx
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def add_switch(x, y, bel=-1):
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@ -1034,20 +1172,32 @@ for wire in range(num_wires):
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info["num_bel_pins"] = num_bel_pins
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info["list_bel_pins"] = ("wire%d_bels" % wire) if num_bel_pins > 0 else None
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pos_xy = None
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first = None
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if wire in wire_xy:
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avg_x, avg_y = 0, 0
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for x, y, n in wire_xy[wire]:
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norm_xy = norm_wire_xy(x, y, n)
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if norm_xy is None:
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continue
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if pos_xy is None:
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pos_xy = norm_xy
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first = (x, y, n)
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elif pos_xy != norm_xy:
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print("Conflicting positions for wire %s: (%d, %d, %s) -> (%d, %d), (%d, %d, %s) -> (%d, %d)" % \
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((info["name"],) + first + pos_xy + (x, y, n) + norm_xy), file=sys.stderr)
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assert 0
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if (pos_xy is None) and (len(wire_xy[wire]) > 1):
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# print("Only 'None' positions for wire %s." % info["name"], file=sys.stderr)
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# assert 0
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pass
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for x, y in wire_xy[wire]:
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avg_x += x
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avg_y += y
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avg_x /= len(wire_xy[wire])
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avg_y /= len(wire_xy[wire])
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info["x"] = int(round(avg_x))
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info["y"] = int(round(avg_y))
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else:
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if pos_xy is None:
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info["x"] = wire_names_r[wire][0]
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info["y"] = wire_names_r[wire][1]
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else:
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info["x"] = pos_xy[0]
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info["y"] = pos_xy[1]
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wireinfo.append(info)
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@ -1108,14 +1258,21 @@ for t in range(num_tile_types):
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bba.l("wire_data_%s" % dev_name, "WireInfoPOD")
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for wire, info in enumerate(wireinfo):
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bba.s(info["name"], "name")
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bba.u32(wire, "netidx")
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bba.u32(info["num_uphill"], "num_uphill")
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bba.u32(info["num_downhill"], "num_downhill")
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bba.r(info["list_uphill"], "pips_uphill")
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bba.r(info["list_downhill"], "pips_downhill")
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bba.u32(info["num_bel_pins"], "num_bel_pins")
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bba.r(info["list_bel_pins"], "bel_pins")
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bba.u32(len(wire_segments[wire]), "num_segments")
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if len(wire_segments[wire]):
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num_segments = 0
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for segs in wire_segments[wire].values():
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num_segments += len(segs)
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bba.u32(num_segments, "num_segments")
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if num_segments:
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bba.r("wire_segments_%d" % wire, "segments")
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else:
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bba.u32(0, "segments")
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@ -1131,24 +1288,25 @@ for wire, info in enumerate(wireinfo):
|
||||
for wire in range(num_wires):
|
||||
if len(wire_segments[wire]):
|
||||
bba.l("wire_segments_%d" % wire, "WireSegmentPOD")
|
||||
for xy, seg in sorted(wire_segments[wire].items()):
|
||||
bba.u8(xy[0], "x")
|
||||
bba.u8(xy[1], "y")
|
||||
bba.u16(gfx_wire_ids["TILE_WIRE_" + seg.upper().replace("/", "_")], "index")
|
||||
for xy, segs in sorted(wire_segments[wire].items()):
|
||||
for seg in segs:
|
||||
bba.u8(xy[0], "x")
|
||||
bba.u8(xy[1], "y")
|
||||
bba.u16(gfx_wire_ids["TILE_WIRE_" + seg.upper().replace("/", "_")], "index")
|
||||
|
||||
bba.l("pip_data_%s" % dev_name, "PipInfoPOD")
|
||||
for info in pipinfo:
|
||||
src_seg = -1
|
||||
src_segname = wire_names_r[info["src"]]
|
||||
if (info["x"], info["y"]) in wire_segments[info["src"]]:
|
||||
src_segname = wire_segments[info["src"]][(info["x"], info["y"])]
|
||||
src_segname = wire_segments[info["src"]][(info["x"], info["y"])][0]
|
||||
src_seg = gfx_wire_ids["TILE_WIRE_" + src_segname.upper().replace("/", "_")]
|
||||
src_segname = src_segname.replace("/", ".")
|
||||
|
||||
dst_seg = -1
|
||||
dst_segname = wire_names_r[info["dst"]]
|
||||
if (info["x"], info["y"]) in wire_segments[info["dst"]]:
|
||||
dst_segname = wire_segments[info["dst"]][(info["x"], info["y"])]
|
||||
dst_segname = wire_segments[info["dst"]][(info["x"], info["y"])][0]
|
||||
dst_seg = gfx_wire_ids["TILE_WIRE_" + dst_segname.upper().replace("/", "_")]
|
||||
dst_segname = dst_segname.replace("/", ".")
|
||||
|
||||
|
||||
49
ice40/gfx.cc
49
ice40/gfx.cc
@ -457,6 +457,42 @@ void gfxTileWire(std::vector<GraphicElement> &g, int x, int y, GfxTileWireId id,
|
||||
}
|
||||
}
|
||||
|
||||
// LC Control for IO and BRAM
|
||||
|
||||
if (id >= TILE_WIRE_FUNC_GLOBAL_CEN && id <= TILE_WIRE_FUNC_GLOBAL_S_R) {
|
||||
int idx = id - TILE_WIRE_FUNC_GLOBAL_CEN;
|
||||
|
||||
el.x1 = x + main_swbox_x2 - 0.005 * (idx + 5);
|
||||
el.x2 = el.x1;
|
||||
el.y1 = y + main_swbox_y1;
|
||||
el.y2 = el.y1 - 0.005 * (idx + 2);
|
||||
g.push_back(el);
|
||||
|
||||
el.y1 = el.y2;
|
||||
el.x2 = x + logic_cell_x2 - 0.005 * (2 - idx + 5);
|
||||
g.push_back(el);
|
||||
|
||||
el.y2 = y + logic_cell_y1;
|
||||
el.x1 = el.x2;
|
||||
g.push_back(el);
|
||||
}
|
||||
|
||||
if (id == TILE_WIRE_FABOUT) {
|
||||
el.y1 = y + main_swbox_y1;
|
||||
el.y2 = el.y1 - 0.005 * 4;
|
||||
el.x1 = x + main_swbox_x2 - 0.005 * 9;
|
||||
el.x2 = el.x1;
|
||||
g.push_back(el);
|
||||
}
|
||||
|
||||
if (id == TILE_WIRE_FUNC_GLOBAL_G0) {
|
||||
el.y1 = y + logic_cell_y1;
|
||||
el.y2 = el.y1 - 0.005 * 4;
|
||||
el.x1 = x + logic_cell_x2 - 0.005 * 3;
|
||||
el.x2 = el.x1;
|
||||
g.push_back(el);
|
||||
}
|
||||
|
||||
// LC Cascade
|
||||
|
||||
if (id >= TILE_WIRE_LUTFF_0_LOUT && id <= TILE_WIRE_LUTFF_6_LOUT) {
|
||||
@ -626,6 +662,19 @@ static bool getWireXY_main(GfxTileWireId id, float &x, float &y)
|
||||
return true;
|
||||
}
|
||||
|
||||
if (id >= TILE_WIRE_FUNC_GLOBAL_CEN && id <= TILE_WIRE_FUNC_GLOBAL_S_R) {
|
||||
int idx = id - TILE_WIRE_FUNC_GLOBAL_CEN;
|
||||
x = main_swbox_x2 - 0.005 * (idx + 5);
|
||||
y = main_swbox_y1;
|
||||
return true;
|
||||
}
|
||||
|
||||
if (id == TILE_WIRE_FABOUT) {
|
||||
x = main_swbox_x2 - 0.005 * 9;
|
||||
y = main_swbox_y1;
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
@ -205,6 +205,13 @@ enum GfxTileWireId
|
||||
TILE_WIRE_LUTFF_GLOBAL_CLK,
|
||||
TILE_WIRE_LUTFF_GLOBAL_S_R,
|
||||
|
||||
TILE_WIRE_FUNC_GLOBAL_CEN,
|
||||
TILE_WIRE_FUNC_GLOBAL_CLK,
|
||||
TILE_WIRE_FUNC_GLOBAL_S_R,
|
||||
|
||||
TILE_WIRE_FUNC_GLOBAL_G0,
|
||||
TILE_WIRE_FABOUT,
|
||||
|
||||
TILE_WIRE_CARRY_IN,
|
||||
TILE_WIRE_CARRY_IN_MUX,
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user