diff --git a/xc7/attosoc.pcf b/xc7/attosoc.pcf new file mode 100644 index 00000000..3ef75a17 --- /dev/null +++ b/xc7/attosoc.pcf @@ -0,0 +1,9 @@ +COMP "led[0]" LOCATE = SITE "M14" LEVEL 1; +COMP "led[1]" LOCATE = SITE "M15" LEVEL 1; +COMP "led[2]" LOCATE = SITE "G14" LEVEL 1; +COMP "led[3]" LOCATE = SITE "D18" LEVEL 1; +COMP "clk" LOCATE = SITE "K17" LEVEL 1; +COMP "pll.mmcm_adv_inst" LOCATE = SITE "MMCME2_ADV_X1Y2" LEVEL 1; +NET "pll.clkin1" PERIOD = 8 nS ; +#PIN "clk_pin" = BEL "clk.PAD" PINNAME PAD; +#PIN "clk_pin" CLOCK_DEDICATED_ROUTE = FALSE; diff --git a/xc7/attosoc.v b/xc7/attosoc.v new file mode 100644 index 00000000..4921e298 --- /dev/null +++ b/xc7/attosoc.v @@ -0,0 +1,127 @@ +/* + * ECP5 PicoRV32 demo + * + * Copyright (C) 2017 Clifford Wolf + * Copyright (C) 2018 David Shah + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +`ifdef PICORV32_V +`error "attosoc.v must be read before picorv32.v!" +`endif + +`define PICORV32_REGS picosoc_regs + +module attosoc ( + input clk, + output reg [7:0] led +); + + reg [5:0] reset_cnt = 0; + wire resetn = &reset_cnt; + + always @(posedge clk) begin + reset_cnt <= reset_cnt + !resetn; + end + + parameter integer MEM_WORDS = 256; + parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory + parameter [31:0] PROGADDR_RESET = 32'h 0000_0000; // ROM at 0x0 + parameter integer ROM_BYTES = 256; + + reg [7:0] rom [0:ROM_BYTES-1]; + wire [31:0] rom_rdata = {rom[mem_addr+3], rom[mem_addr+2], rom[mem_addr+1], rom[mem_addr+0]}; + initial $readmemh("firmware.hex", rom); + + wire mem_valid; + wire mem_instr; + wire mem_ready; + wire [31:0] mem_addr; + wire [31:0] mem_wdata; + wire [3:0] mem_wstrb; + wire [31:0] mem_rdata; + + wire rom_ready = mem_valid && mem_addr[31:24] == 8'h00; + + wire iomem_valid; + wire iomem_ready; + wire [31:0] iomem_addr; + wire [31:0] iomem_wdata; + wire [3:0] iomem_wstrb; + wire [31:0] iomem_rdata; + + assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01); + assign iomem_ready = 1'b1; + assign iomem_wstrb = mem_wstrb; + assign iomem_addr = mem_addr; + assign iomem_wdata = mem_wdata; + + wire [31:0] spimemio_cfgreg_do; + + + always @(posedge clk) + if (iomem_valid && iomem_wstrb[0]) + led <= iomem_wdata[7:0]; + + assign mem_ready = (iomem_valid && iomem_ready) || rom_ready; + + assign mem_rdata = rom_rdata; + + picorv32 #( + .STACKADDR(STACKADDR), + .PROGADDR_RESET(PROGADDR_RESET), + .PROGADDR_IRQ(32'h 0000_0000), + .BARREL_SHIFTER(0), + .COMPRESSED_ISA(0), + .ENABLE_MUL(0), + .ENABLE_DIV(0), + .ENABLE_IRQ(0), + .ENABLE_IRQ_QREGS(0) + ) cpu ( + .clk (clk ), + .resetn (resetn ), + .mem_valid (mem_valid ), + .mem_instr (mem_instr ), + .mem_ready (mem_ready ), + .mem_addr (mem_addr ), + .mem_wdata (mem_wdata ), + .mem_wstrb (mem_wstrb ), + .mem_rdata (mem_rdata ) + ); + + + +endmodule + +// Implementation note: +// Replace the following two modules with wrappers for your SRAM cells. + +module picosoc_regs ( + input clk, wen, + input [5:0] waddr, + input [5:0] raddr1, + input [5:0] raddr2, + input [31:0] wdata, + output [31:0] rdata1, + output [31:0] rdata2 +); + reg [31:0] regs [0:31]; + + always @(posedge clk) + if (wen) regs[waddr[4:0]] <= wdata; + + assign rdata1 = regs[raddr1[4:0]]; + assign rdata2 = regs[raddr2[4:0]]; +endmodule diff --git a/xc7/attosoc.ys b/xc7/attosoc.ys new file mode 100644 index 00000000..105728c9 --- /dev/null +++ b/xc7/attosoc.ys @@ -0,0 +1,56 @@ +read_verilog attosoc_top.v +read_verilog attosoc.v +read_verilog picorv32.v +read_verilog 125MHz_to_60MHz.v + +#synth_xilinx -top picorv32 + +#begin: + read_verilog -lib +/xilinx/cells_sim.v + read_verilog -lib +/xilinx/cells_xtra.v +# read_verilog -lib +/xilinx/brams_bb.v +# read_verilog -lib +/xilinx/drams_bb.v + hierarchy -check -top top + +#flatten: (only if -flatten) + proc + flatten + +#coarse: + synth -run coarse + +#bram: +# memory_bram -rules +/xilinx/brams.txt +# techmap -map +/xilinx/brams_map.v +# +#dram: +# memory_bram -rules +/xilinx/drams.txt +# techmap -map +/xilinx/drams_map.v + +fine: + opt -fast -full + memory_map + dffsr2dff +# dff2dffe + opt -full + techmap -map +/techmap.v #-map +/xilinx/arith_map.v + opt -fast + +map_luts: + abc -luts 2:2,3,6:5 #,10,20 [-dff] + clean + +map_cells: + techmap -map +/xilinx/cells_map.v + dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT + clean + +check: + hierarchy -check + stat + check -noinit + +#edif: (only if -edif) +# write_edif + +write_json attosoc.json diff --git a/xc7/attosoc_top.v b/xc7/attosoc_top.v new file mode 100644 index 00000000..5611f1d2 --- /dev/null +++ b/xc7/attosoc_top.v @@ -0,0 +1,15 @@ +module top ( + input clk, + output [3:0] led +); + + (* keep *) + wire led_unused; + + wire gclk; + //clk_wiz_v3_6 pll(.CLK_IN1(clk), .CLK_OUT1(gclk)); + assign gclk = clk; + attosoc soc(.clk(gclk), .led({led_unused, led})); + +endmodule +