diff --git a/common/timing.cc b/common/timing.cc index 47c82a03..5ffd4ea7 100644 --- a/common/timing.cc +++ b/common/timing.cc @@ -62,12 +62,13 @@ static delay_t follow_user_port(Context *ctx, PortRef &user, int path_length, if (value < user.budget) { user.budget = value; } + return value; } static delay_t follow_net(Context *ctx, NetInfo *net, int path_length, delay_t slack) { - delay_t net_budget = slack / path_length; + delay_t net_budget = slack / (path_length + 1); for (auto &usr : net->users) { net_budget = std::min( net_budget, follow_user_port(ctx, usr, path_length + 1, slack)); @@ -77,6 +78,7 @@ static delay_t follow_net(Context *ctx, NetInfo *net, int path_length, void assign_budget(Context *ctx, float default_clock) { + log_info("Annotating ports with timing budgets\n"); for (auto cell : ctx->cells) { for (auto port : cell.second->ports) { if (port.second.type == PORT_OUT) { diff --git a/ice40/arch.cc b/ice40/arch.cc index 7baaef8d..ba02ff9f 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -21,7 +21,7 @@ #include #include "log.h" #include "nextpnr.h" - +#include "util.h" NEXTPNR_NAMESPACE_BEGIN // ----------------------------------------------------------------------- @@ -414,26 +414,39 @@ std::vector Arch::getPipGraphics(PipId pip) const std::vector ret; // FIXME return ret; -} +}; // ----------------------------------------------------------------------- bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const { - // TODO + if (cell->type == id("ICESTORM_LC")) { + if (fromPort == id("I0") || fromPort == id("I1") || + fromPort == id("I2") || fromPort == id("I3")) { + if (toPort == id("O") || toPort == id("LO")) { + delay = 450; + return true; + } + } + } return false; } IdString Arch::getPortClock(const CellInfo *cell, IdString port) const { - // TODO + if (cell->type == id("ICESTORM_LC") && + bool_or_default(cell->params, id("DFF_ENABLE"))) { + if (port != id("LO") && port != id("CIN") && port != id("COUT")) + return id("CLK"); + } return IdString(); } bool Arch::isClockPort(const CellInfo *cell, IdString port) const { - // TODO + if (cell->type == id("ICESTORM_LC") && port == id("CLK")) + return true; return false; } diff --git a/ice40/main.cc b/ice40/main.cc index 802a08b8..70d88946 100644 --- a/ice40/main.cc +++ b/ice40/main.cc @@ -36,6 +36,7 @@ #include "pybindings.h" #include "route.h" #include "version.h" +#include "timing.h" void svg_dump_el(const GraphicElement &el) { @@ -232,7 +233,7 @@ int main(int argc, char *argv[]) if (!pack_design(&ctx) && !ctx.force) log_error("Packing design failed.\n"); - + assign_budget(&ctx); print_utilisation(&ctx); if (!vm.count("pack-only")) {