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ice40: Update examples to use packer/pcf

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Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-06-13 12:55:08 +02:00
parent 1e314cc0ce
commit 4694c6aae7
10 changed files with 37 additions and 398 deletions
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6
ice40/blinky.pcf Normal file
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@ -0,0 +1,6 @@
set_io led1 99
set_io led2 98
set_io led3 97
set_io led4 96
set_io led5 95
set_io clki 21

2
ice40/blinky.sh Normal file → Executable file
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@ -1,7 +1,7 @@
#!/bin/bash
set -ex
yosys blinky.ys
../nextpnr-ice40 --json blinky.json --asc blinky.asc
../nextpnr-ice40 --json blinky.json --pcf blinky.pcf --asc blinky.asc
icepack blinky.asc blinky.bin
icebox_vlog blinky.asc > blinky_chip.v
iverilog -o blinky_tb blinky_chip.v blinky_tb.v

123
ice40/blinky.v
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@ -1,128 +1,17 @@
module blinky (
input clk_pin,
output led1_pin,
output led2_pin,
output led3_pin,
output led4_pin,
output led5_pin
input clki,
output led1,
output led2,
output led3,
output led4,
output led5
);
wire clk, clki;
SB_GB clk_gb (
.USER_SIGNAL_TO_GLOBAL_BUFFER(clki),
.GLOBAL_BUFFER_OUTPUT(clk)
);
wire led1, led2, led3, led4, led5;
(* BEL="13_12_io1" *)
SB_IO #(
.PIN_TYPE(6'b 0110_01),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0)
) led1_iob (
.PACKAGE_PIN(led1_pin),
.LATCH_INPUT_VALUE(),
.CLOCK_ENABLE(),
.INPUT_CLK(),
.OUTPUT_CLK(),
.OUTPUT_ENABLE(),
.D_OUT_0(led1),
.D_OUT_1(),
.D_IN_0(),
.D_IN_1()
);
(* BEL="13_12_io0" *)
SB_IO #(
.PIN_TYPE(6'b 0110_01),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0)
) led2_iob (
.PACKAGE_PIN(led2_pin),
.LATCH_INPUT_VALUE(),
.CLOCK_ENABLE(),
.INPUT_CLK(),
.OUTPUT_CLK(),
.OUTPUT_ENABLE(),
.D_OUT_0(led2),
.D_OUT_1(),
.D_IN_0(),
.D_IN_1()
);
(* BEL="13_11_io1" *)
SB_IO #(
.PIN_TYPE(6'b 0110_01),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0)
) led3_iob (
.PACKAGE_PIN(led3_pin),
.LATCH_INPUT_VALUE(),
.CLOCK_ENABLE(),
.INPUT_CLK(),
.OUTPUT_CLK(),
.OUTPUT_ENABLE(),
.D_OUT_0(led3),
.D_OUT_1(),
.D_IN_0(),
.D_IN_1()
);
(* BEL="13_11_io0" *)
SB_IO #(
.PIN_TYPE(6'b 0110_01),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0)
) led4_iob (
.PACKAGE_PIN(led4_pin),
.LATCH_INPUT_VALUE(),
.CLOCK_ENABLE(),
.INPUT_CLK(),
.OUTPUT_CLK(),
.OUTPUT_ENABLE(),
.D_OUT_0(led4),
.D_OUT_1(),
.D_IN_0(),
.D_IN_1()
);
(* BEL="13_9_io1" *)
SB_IO #(
.PIN_TYPE(6'b 0110_01),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0)
) led5_iob (
.PACKAGE_PIN(led5_pin),
.LATCH_INPUT_VALUE(),
.CLOCK_ENABLE(),
.INPUT_CLK(),
.OUTPUT_CLK(),
.OUTPUT_ENABLE(),
.D_OUT_0(led5),
.D_OUT_1(),
.D_IN_0(),
.D_IN_1()
);
(* BEL="0_8_io1" *)
SB_IO #(
.PIN_TYPE(6'b 0000_01),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0)
) clk_iob (
.PACKAGE_PIN(clk_pin),
.LATCH_INPUT_VALUE(),
.CLOCK_ENABLE(),
.INPUT_CLK(),
.OUTPUT_CLK(),
.OUTPUT_ENABLE(),
.D_OUT_0(),
.D_OUT_1(),
.D_IN_0(clki),
.D_IN_1()
);
localparam BITS = 5;
localparam LOG2DELAY = 22;

8
ice40/blinky.ys
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@ -1,9 +1,3 @@
read_verilog blinky.v
read_verilog -lib +/ice40/cells_sim.v
synth -top blinky
abc -lut 4
techmap -map blinky_map.v
splitnets
opt_clean
stat
synth_ice40 -top blinky -nocarry
write_json blinky.json

86
ice40/blinky_map.v
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@ -1,86 +0,0 @@
module \$_DFF_P_ (input D, C, output Q);
ICESTORM_LC #(
.LUT_INIT(2),
.NEG_CLK(0),
.CARRY_ENABLE(0),
.DFF_ENABLE(1),
.SET_NORESET(0),
.ASYNC_SR(0)
) _TECHMAP_REPLACE_ (
.I0(D),
.CLK(C),
.O(Q),
.I1(),
.I2(),
.I3(),
.CIN(),
.CEN(),
.SR(),
.LO(),
.COUT()
);
endmodule
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
ICESTORM_LC #(
.LUT_INIT(LUT),
.NEG_CLK(0),
.CARRY_ENABLE(0),
.DFF_ENABLE(0),
.SET_NORESET(0),
.ASYNC_SR(0)
) _TECHMAP_REPLACE_ (
.I0(A[0]), .I1(), .I2(), .I3(), .O(Y),
.CLK(), .CIN(), .CEN(), .SR(), .LO(), .COUT()
);
end
if (WIDTH == 2) begin
ICESTORM_LC #(
.LUT_INIT(LUT),
.NEG_CLK(0),
.CARRY_ENABLE(0),
.DFF_ENABLE(0),
.SET_NORESET(0),
.ASYNC_SR(0)
) _TECHMAP_REPLACE_ (
.I0(A[0]), .I1(A[1]), .I2(), .I3(), .O(Y),
.CLK(), .CIN(), .CEN(), .SR(), .LO(), .COUT()
);
end
if (WIDTH == 3) begin
ICESTORM_LC #(
.LUT_INIT(LUT),
.NEG_CLK(0),
.CARRY_ENABLE(0),
.DFF_ENABLE(0),
.SET_NORESET(0),
.ASYNC_SR(0)
) _TECHMAP_REPLACE_ (
.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(), .O(Y),
.CLK(), .CIN(), .CEN(), .SR(), .LO(), .COUT()
);
end
if (WIDTH == 4) begin
ICESTORM_LC #(
.LUT_INIT(LUT),
.NEG_CLK(0),
.CARRY_ENABLE(0),
.DFF_ENABLE(0),
.SET_NORESET(0),
.ASYNC_SR(0)
) _TECHMAP_REPLACE_ (
.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]), .O(Y),
.CLK(), .CIN(), .CEN(), .SR(), .LO(), .COUT()
);
end
endgenerate
endmodule

3
ice40/blinky_nopack.ys
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@ -1,3 +0,0 @@
read_verilog blinky.v
synth_ice40 -nocarry -top blinky
write_json blinky_nopack.json

8
ice40/blinky_noyspack.sh
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@ -1,8 +0,0 @@
#!/bin/bash
set -ex
yosys blinky_nopack.ys
../nextpnr-ice40 --json blinky_nopack.json --asc blinky.asc --pack
icepack blinky.asc blinky.bin
icebox_vlog blinky.asc > blinky_chip.v
iverilog -o blinky_tb blinky_chip.v blinky_tb.v
vvp -N ./blinky_tb

5
ice40/chipdb.py
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@ -410,16 +410,17 @@ packageinfo = []
for package in packages:
name, pins = package
safename = re.sub("[^A-Za-z0-9]", "_", name)
pins_info = []
for pin in pins:
pinname, x, y, z = pin
pin_bel = "%d_%d_io%d" % (x, y, z)
bel_idx = bel_name.index(pin_bel)
pins_info.append('{"%s", %d}' % (pinname, bel_idx))
print("static PackagePinPOD package_%s_pins[%d] = {" % (name, len(pins_info)))
print("static PackagePinPOD package_%s_pins[%d] = {" % (safename, len(pins_info)))
print(",\n".join(pins_info))
print("};")
packageinfo.append('{"%s", %d, package_%s_pins}' % (name, len(pins_info), name))
packageinfo.append('{"%s", %d, package_%s_pins}' % (name, len(pins_info), safename))
tilegrid = []
for y in range(dev_height):

9
ice40/icebreaker.pcf Normal file
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@ -0,0 +1,9 @@
set_io led1 27
set_io led2 25
set_io led3 21
set_io led4 23
set_io led5 26
set_io clki 35
set_io btn1 20
set_io btn2 19
set_io btn3 18

185
ice40/icebreaker.v
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@ -1,179 +1,16 @@
module icebreaker (
input clk_pin,
input btn1_pin,
input btn2_pin,
input btn3_pin,
output led1_pin,
output led2_pin,
output led3_pin,
output led4_pin,
output led5_pin
input clki,
input btn1,
input btn2,
input btn3,
output led1,
output led2,
output led3,
output led4,
output led5
);
wire clk, clk_pre, led1, led2, led3, led4, led5, btn1, btn2, btn3;
(* BEL="18_31_io1" *) //27
SB_IO #(
.PIN_TYPE(6'b 0110_01),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0)
) led1_iob (
.PACKAGE_PIN(led1_pin),
.LATCH_INPUT_VALUE(),
.CLOCK_ENABLE(),
.INPUT_CLK(),
.OUTPUT_CLK(),
.OUTPUT_ENABLE(),
.D_OUT_0(led1),
.D_OUT_1(),
.D_IN_0(),
.D_IN_1()
);
(* BEL="19_31_io1" *) //25
SB_IO #(
.PIN_TYPE(6'b 0110_01),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0)
) led2_iob (
.PACKAGE_PIN(led2_pin),
.LATCH_INPUT_VALUE(),
.CLOCK_ENABLE(),
.INPUT_CLK(),
.OUTPUT_CLK(),
.OUTPUT_ENABLE(),
.D_OUT_0(led2),
.D_OUT_1(),
.D_IN_0(),
.D_IN_1()
);
(* BEL="18_0_io1" *) //21
SB_IO #(
.PIN_TYPE(6'b 0110_01),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0)
) led3_iob (
.PACKAGE_PIN(led3_pin),
.LATCH_INPUT_VALUE(),
.CLOCK_ENABLE(),
.INPUT_CLK(),
.OUTPUT_CLK(),
.OUTPUT_ENABLE(),
.D_OUT_0(led3),
.D_OUT_1(),
.D_IN_0(),
.D_IN_1()
);
(* BEL="19_31_io0" *) //23
SB_IO #(
.PIN_TYPE(6'b 0110_01),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0)
) led4_iob (
.PACKAGE_PIN(led4_pin),
.LATCH_INPUT_VALUE(),
.CLOCK_ENABLE(),
.INPUT_CLK(),
.OUTPUT_CLK(),
.OUTPUT_ENABLE(),
.D_OUT_0(led4),
.D_OUT_1(),
.D_IN_0(),
.D_IN_1()
);
(* BEL="18_31_io0" *) //26
SB_IO #(
.PIN_TYPE(6'b 0110_01),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0)
) led5_iob (
.PACKAGE_PIN(led5_pin),
.LATCH_INPUT_VALUE(),
.CLOCK_ENABLE(),
.INPUT_CLK(),
.OUTPUT_CLK(),
.OUTPUT_ENABLE(),
.D_OUT_0(led5),
.D_OUT_1(),
.D_IN_0(),
.D_IN_1()
);
(* BEL="12_31_io1" *) //35
SB_IO #(
.PIN_TYPE(6'b 0000_01),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0)
) clk_iob (
.PACKAGE_PIN(clk_pin),
.LATCH_INPUT_VALUE(),
.CLOCK_ENABLE(),
.INPUT_CLK(),
.OUTPUT_CLK(),
.OUTPUT_ENABLE(),
.D_OUT_0(),
.D_OUT_1(),
.D_IN_0(clk_pre),
.D_IN_1()
);
(* BEL="19_0_io1" *) //20
SB_IO #(
.PIN_TYPE(6'b 0000_01),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0)
) btn1_iob (
.PACKAGE_PIN(btn1_pin),
.LATCH_INPUT_VALUE(),
.CLOCK_ENABLE(),
.INPUT_CLK(),
.OUTPUT_CLK(),
.OUTPUT_ENABLE(),
.D_OUT_0(),
.D_OUT_1(),
.D_IN_0(btn1),
.D_IN_1()
);
(* BEL="21_0_io1" *) //19
SB_IO #(
.PIN_TYPE(6'b 0000_01),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0)
) btn2_iob (
.PACKAGE_PIN(btn2_pin),
.LATCH_INPUT_VALUE(),
.CLOCK_ENABLE(),
.INPUT_CLK(),
.OUTPUT_CLK(),
.OUTPUT_ENABLE(),
.D_OUT_0(),
.D_OUT_1(),
.D_IN_0(btn2),
.D_IN_1()
);
(* BEL="22_0_io1" *) //18
SB_IO #(
.PIN_TYPE(6'b 0000_01),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0)
) btn3_iob (
.PACKAGE_PIN(btn3_pin),
.LATCH_INPUT_VALUE(),
.CLOCK_ENABLE(),
.INPUT_CLK(),
.OUTPUT_CLK(),
.OUTPUT_ENABLE(),
.D_OUT_0(),
.D_OUT_1(),
.D_IN_0(btn3),
.D_IN_1()
);
SB_GB clk_gb(.USER_SIGNAL_TO_GLOBAL_BUFFER(clk_pre), .GLOBAL_BUFFER_OUTPUT(clk));
wire clk;
SB_GB clk_gb(.USER_SIGNAL_TO_GLOBAL_BUFFER(clki), .GLOBAL_BUFFER_OUTPUT(clk));
localparam BITS = 5;
localparam LOG2DELAY = 22;