fpga_interchange: add test data for new architectures
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
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36
fpga_interchange/examples/devices/xc7a100t/test_data.yaml
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36
fpga_interchange/examples/devices/xc7a100t/test_data.yaml
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pip_test:
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- src_wire: CLBLM_R_X11Y93/CLBLM_L_D3
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dst_wire: SLICE_X15Y93.SLICEL/D3
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pip_chain_test:
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- wires:
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- $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
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- $CONSTANTS_X0Y0/$GND_NODE
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- TIEOFF_X3Y145.TIEOFF/$GND_SITE_WIRE
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- TIEOFF_X3Y145.TIEOFF/HARD0GND_HARD0
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- INT_R_X3Y145/GND_WIRE
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- wires:
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- $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
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- $CONSTANTS_X0Y0/$VCC_NODE
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- TIEOFF_X3Y145.TIEOFF/$VCC_SITE_WIRE
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- TIEOFF_X3Y145.TIEOFF/HARD1VCC_HARD1
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- INT_R_X3Y145/VCC_WIRE
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- wires:
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- $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
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- $CONSTANTS_X0Y0/$VCC_NODE
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- SLICE_X3Y145.SLICEL/$VCC_SITE_WIRE
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- SLICE_X3Y145.SLICEL/CEUSEDVCC_HARD1
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- wires:
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- $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
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- $CONSTANTS_X0Y0/$GND_NODE
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- SLICE_X3Y145.SLICEL/$GND_SITE_WIRE
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- SLICE_X3Y145.SLICEL/SRUSEDGND_HARD0
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bel_pin_test:
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- bel: SLICE_X15Y93.SLICEL/D6LUT
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pin: A3
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wire: SLICE_X15Y93.SLICEL/D3
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- bel: $CONSTANTS_X0Y0.$CONSTANTS/GND
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pin: G
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wire: $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
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- bel: $CONSTANTS_X0Y0.$CONSTANTS/VCC
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pin: P
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wire: $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
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36
fpga_interchange/examples/devices/xc7a200t/test_data.yaml
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36
fpga_interchange/examples/devices/xc7a200t/test_data.yaml
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@ -0,0 +1,36 @@
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pip_test:
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- src_wire: CLBLM_R_X11Y93/CLBLM_L_D3
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dst_wire: SLICE_X15Y93.SLICEL/D3
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pip_chain_test:
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- wires:
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- $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
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- $CONSTANTS_X0Y0/$GND_NODE
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- TIEOFF_X3Y145.TIEOFF/$GND_SITE_WIRE
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- TIEOFF_X3Y145.TIEOFF/HARD0GND_HARD0
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- INT_R_X3Y145/GND_WIRE
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- wires:
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- $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
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- $CONSTANTS_X0Y0/$VCC_NODE
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- TIEOFF_X3Y145.TIEOFF/$VCC_SITE_WIRE
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- TIEOFF_X3Y145.TIEOFF/HARD1VCC_HARD1
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- INT_R_X3Y145/VCC_WIRE
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- wires:
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- $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
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- $CONSTANTS_X0Y0/$VCC_NODE
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- SLICE_X3Y145.SLICEL/$VCC_SITE_WIRE
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- SLICE_X3Y145.SLICEL/CEUSEDVCC_HARD1
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- wires:
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- $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
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- $CONSTANTS_X0Y0/$GND_NODE
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- SLICE_X3Y145.SLICEL/$GND_SITE_WIRE
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- SLICE_X3Y145.SLICEL/SRUSEDGND_HARD0
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bel_pin_test:
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- bel: SLICE_X15Y93.SLICEL/D6LUT
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pin: A3
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wire: SLICE_X15Y93.SLICEL/D3
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- bel: $CONSTANTS_X0Y0.$CONSTANTS/GND
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pin: G
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wire: $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
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- bel: $CONSTANTS_X0Y0.$CONSTANTS/VCC
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pin: P
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wire: $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
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36
fpga_interchange/examples/devices/xc7z010/test_data.yaml
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36
fpga_interchange/examples/devices/xc7z010/test_data.yaml
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@ -0,0 +1,36 @@
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pip_test:
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- src_wire: CLBLM_L_X8Y69/CLBLM_L_D3
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dst_wire: SLICE_X11Y69.SLICEL/D3
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pip_chain_test:
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- wires:
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- $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
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- $CONSTANTS_X0Y0/$GND_NODE
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- TIEOFF_X9Y69.TIEOFF/$GND_SITE_WIRE
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- TIEOFF_X9Y69.TIEOFF/HARD0GND_HARD0
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- INT_L_X8Y69/GND_WIRE
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- wires:
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- $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
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- $CONSTANTS_X0Y0/$VCC_NODE
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- TIEOFF_X9Y69.TIEOFF/$VCC_SITE_WIRE
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- TIEOFF_X9Y69.TIEOFF/HARD1VCC_HARD1
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- INT_L_X8Y69/VCC_WIRE
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- wires:
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- $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
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- $CONSTANTS_X0Y0/$VCC_NODE
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- SLICE_X11Y69.SLICEL/$VCC_SITE_WIRE
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- SLICE_X11Y69.SLICEL/CEUSEDVCC_HARD1
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- wires:
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- $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
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- $CONSTANTS_X0Y0/$GND_NODE
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- SLICE_X11Y69.SLICEL/$GND_SITE_WIRE
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- SLICE_X11Y69.SLICEL/SRUSEDGND_HARD0
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bel_pin_test:
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- bel: SLICE_X14Y63.SLICEL/D6LUT
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pin: A3
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wire: SLICE_X14Y63.SLICEL/D3
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- bel: $CONSTANTS_X0Y0.$CONSTANTS/GND
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pin: G
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wire: $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
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- bel: $CONSTANTS_X0Y0.$CONSTANTS/VCC
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pin: P
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wire: $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
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