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interchange: tests: counter: emit carries for xc7

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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi 2021-06-10 12:41:47 +02:00
parent 104536b7aa
commit 490ca794c5
2 changed files with 6 additions and 4 deletions
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8
fpga_interchange/examples/tests/counter/counter.v
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@ -1,13 +1,15 @@
module top(input clk, input rst, output [7:4] io_led);
reg [31:0] counter = 32'b0;
localparam SIZE = 32;
assign io_led = counter >> 22;
reg [SIZE-1:0] counter = SIZE'b0;
assign io_led = {counter[SIZE-1], counter[25:23]};
always @(posedge clk)
begin
if(rst)
counter <= 32'b0;
counter <= SIZE'b0;
else
counter <= counter + 1;
end

2
fpga_interchange/examples/tests/counter/run_xilinx.tcl
View File

@ -2,7 +2,7 @@ yosys -import
read_verilog $::env(SOURCES)
synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
synth_xilinx -nolutram -nowidelut -nosrl -nodsp
techmap -map $::env(TECHMAP)
# opt_expr -undriven makes sure all nets are driven, if only by the $undef