interchange/nexus: Add counter example

Signed-off-by: gatecat <gatecat@ds0.me>

fpga_interchange/examples/boards/CMakeLists.txt

@@ -32,3 +32,11 @@ add_board(
     device xc7z010
     package clg400
 )
+
+# This isn't a real board, all the real boards currently available use the LIFCL-40 but the LIFCL-17 speeds up runtime for testing
+add_board(
+    name lifcl17
+    device_family nexus
+    device LIFCL-17
+    package QFN72
+)

fpga_interchange/examples/remap_nexus.v

@@ -0,0 +1,4 @@
+// Inverter support is still a TODO
+module INV(input A, output Z);
+	LUT4 #(.INIT("0x5555")) _TECHMAP_REPLACE_ (.A(A), .B(1'b1), .C(1'b1), .D(1'b1), .Z(Z));
+endmodule

fpga_interchange/examples/tests.cmake

@@ -321,6 +321,7 @@ function(add_interchange_group_test)
     #    sources <sources list>
     #    [top <top name>]
     #    [techmap <techmap file>]
+    #    [skip_dcp]
     # )
     #
     # Generates targets to run desired tests over multiple devices.
@@ -340,7 +341,7 @@ function(add_interchange_group_test)
     # Note: it is assumed that there exists an XDC file for each board, with the following naming
     #       convention: <board>.xdc
 
-    set(options output_fasm)
+    set(options output_fasm skip_dcp)
     set(oneValueArgs name family tcl top techmap)
     set(multiValueArgs sources board_list)
 
@@ -359,12 +360,17 @@ function(add_interchange_group_test)
     set(techmap ${add_interchange_group_test_techmap})
     set(sources ${add_interchange_group_test_sources})
     set(output_fasm ${add_interchange_group_test_output_fasm})
+    set(skip_dcp ${add_interchange_group_test_skip_dcp})
 
     set(output_fasm_arg "")
     if(output_fasm)
         set(output_fasm_arg "output_fasm")
     endif()
 
+    set(skip_dcp_arg "")
+    if(skip_dcp)
+        set(skip_dcp_arg "skip_dcp")
+    endif()
 
     if (NOT DEFINED top)
         # Setting default top value
@@ -388,6 +394,7 @@ function(add_interchange_group_test)
             top ${top}
             techmap ${techmap}
             ${output_fasm_arg}
+            ${skip_dcp_arg}
         )
     endforeach()
 endfunction()

fpga_interchange/examples/tests/counter/CMakeLists.txt

@@ -2,8 +2,18 @@ add_interchange_group_test(
     name counter
     family ${family}
     board_list basys3 arty35t arty100t zybo
-    tcl run.tcl
+    tcl run_xilinx.tcl
     sources counter.v
-    techmap ../../remap.v
+    techmap ../../remap_xilinx.v
     output_fasm
 )
+
+add_interchange_group_test(
+    name counter
+    family ${family}
+    board_list lifcl17
+    tcl run_nexus.tcl
+    sources counter.v
+    techmap ../../remap_nexus.v
+    skip_dcp
+)

fpga_interchange/examples/tests/counter/lifcl17.xdc

@@ -0,0 +1,14 @@
+## lifcl17 pins for testing based on breakout board
+set_property PACKAGE_PIN 55 [get_ports clk]
+set_property PACKAGE_PIN 57 [get_ports rst]
+set_property PACKAGE_PIN 56 [get_ports io_led[4]]
+set_property PACKAGE_PIN 59 [get_ports io_led[5]]
+set_property PACKAGE_PIN 60 [get_ports io_led[6]]
+set_property PACKAGE_PIN 61 [get_ports io_led[7]]
+
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports rst]
+set_property IOSTANDARD LVCMOS33 [get_ports io_led[4]]
+set_property IOSTANDARD LVCMOS33 [get_ports io_led[5]]
+set_property IOSTANDARD LVCMOS33 [get_ports io_led[6]]
+set_property IOSTANDARD LVCMOS33 [get_ports io_led[7]]

fpga_interchange/examples/tests/counter/run_nexus.tcl

@@ -0,0 +1,15 @@
+yosys -import
+
+read_verilog $::env(SOURCES)
+
+synth_nexus -nolutram -nowidelut -nobram -noccu2 -nodsp
+techmap -max_iter 1 -map $::env(TECHMAP)
+
+# opt_expr -undriven makes sure all nets are driven, if only by the $undef
+# net.
+opt_expr -undriven
+opt_clean
+
+setundef -zero -params
+
+write_json $::env(OUT_JSON)