ecp5: Add TSHX2DQSA support
Signed-off-by: David Shah <dave@ds0.me>
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82ad10a395
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@ -1887,10 +1887,10 @@ class Ecp5Packer
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process_dqs_port(ci, pio, iol, id_WRPNTR1);
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process_dqs_port(ci, pio, iol, id_WRPNTR0);
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packed_cells.insert(cell.first);
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} else if (ci->type == ctx->id("TSHX2DQA")) {
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} else if (ci->type == ctx->id("TSHX2DQA") || ci->type == ctx->id("TSHX2DQSA")) {
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CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_T, true);
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if (pio == nullptr)
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log_error("TSHX2DQA '%s' Q output must be connected only to a top level tristate\n",
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log_error("%s '%s' Q output must be connected only to a top level tristate\n", ci->type.c_str(ctx),
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ci->name.c_str(ctx));
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CellInfo *iol;
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if (pio_iologic.count(pio->name))
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@ -1909,10 +1909,11 @@ class Ecp5Packer
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set_iologic_lsr(iol, ci, ctx->id("RST"), false);
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replace_port(ci, ctx->id("T0"), iol, id_TSDATA0);
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replace_port(ci, ctx->id("T1"), iol, id_TSDATA1);
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process_dqs_port(ci, pio, iol, id_DQSW270);
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process_dqs_port(ci, pio, iol, ci->type == ctx->id("TSHX2DQSA") ? id_DQSW : id_DQSW270);
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iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
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iol->params[ctx->id("MTDDRX.MODE")] = "MTSHX2";
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iol->params[ctx->id("MIDDRX_MODDRX.WRCLKMUX")] = "DQSW270";
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iol->params[ctx->id("MTDDRX.DQSW_INVERT")] = ci->type == ctx->id("TSHX2DQSA") ? "ENABLED" : "DISABLED";
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iol->params[ctx->id("MIDDRX_MODDRX.WRCLKMUX")] = ci->type == ctx->id("TSHX2DQSA") ? "DQSW" : "DQSW270";
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iol->params[ctx->id("IOLTOMUX")] = "TDDR";
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packed_cells.insert(cell.first);
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}
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