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changed API and added tile wire id in db

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This commit is contained in:
Miodrag Milanovic 2024-03-19 12:35:09 +01:00
parent 49c0d27665
commit 49f098ad51
9 changed files with 218 additions and 42 deletions
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28
himbaechel/arch.cc
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@ -503,38 +503,28 @@ IdString Arch::get_tile_type(int tile) const
std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
{
uint32_t flags = uarch->gfxAttributes();
bool invert_y = flags & GfxFlags::FLAG_INVERT_Y;
std::vector<GraphicElement> ret;
if (flags & GfxFlags::FLAG_SHOW_BEL && decal.type == DecalId::TYPE_BEL) {
if (decal.type == DecalId::TYPE_BEL) {
BelId bel(decal.tile, decal.index);
Loc loc = getBelLocation(bel);
if (invert_y)
loc.y = getGridDimY() - loc.y - 1;
GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
uarch->gfxTileBel(ret, loc.x, loc.y, loc.z, getGridDimX(), getGridDimY(), getBelType(bel), style);
} else if (flags & GfxFlags::FLAG_SHOW_WIRE && decal.type == DecalId::TYPE_WIRE) {
uarch->drawBel(ret, style, getBelType(bel), getBelLocation(bel));
} else if (decal.type == DecalId::TYPE_WIRE) {
WireId wire(decal.tile, decal.index);
auto wire_type = getWireType(wire);
GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
Loc loc;
tile_xy(chip_info, wire.tile, loc.x, loc.y);
if (invert_y)
loc.y = getGridDimY() - loc.y - 1;
int32_t tilewire = chip_wire_info(chip_info, wire).flags;
uarch->gfxTileWire(ret, loc.x, loc.y, getGridDimX(), getGridDimY(), wire_type, tilewire, style);
} else if (flags & GfxFlags::FLAG_SHOW_PIP && decal.type == DecalId::TYPE_PIP) {
int32_t tilewire = chip_wire_info(chip_info, wire).tile_wire;
uarch->drawWire(ret, style, loc, wire_type, tilewire);
} else if (decal.type == DecalId::TYPE_PIP) {
PipId pip(decal.tile, decal.index);
WireId src_wire = getPipSrcWire(pip);
WireId dst_wire = getPipDstWire(pip);
Loc loc = getPipLocation(pip);
if (invert_y)
loc.y = getGridDimY() - loc.y - 1;
int32_t src_id = chip_wire_info(chip_info, src_wire).flags;
int32_t dst_id = chip_wire_info(chip_info, dst_wire).flags;
int32_t src_id = chip_wire_info(chip_info, src_wire).tile_wire;
int32_t dst_id = chip_wire_info(chip_info, dst_wire).tile_wire;
GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_HIDDEN;
uarch->gfxTilePip(ret, loc.x, loc.y, getGridDimX(), getGridDimY(), src_wire, getWireType(src_wire), src_id, dst_wire,
getWireType(dst_wire), dst_id, style);
uarch->drawPip(ret, style, loc, src_wire, getWireType(src_wire), src_id, dst_wire, getWireType(dst_wire), dst_id);
}
return ret;
}

1
himbaechel/chipdb.h
View File

@ -62,6 +62,7 @@ NPNR_PACKED_STRUCT(struct BelPinRefPOD {
NPNR_PACKED_STRUCT(struct TileWireDataPOD {
int32_t name;
int32_t wire_type;
int32_t tile_wire;
int32_t const_value;
int32_t flags; // 32 bits of arbitrary data
int32_t timing_idx; // used only when the wire is not part of a node, otherwise node idx applies

13
himbaechel/himbaechel_api.h
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@ -114,17 +114,12 @@ struct HimbaechelAPI
std::vector<std::pair<CellInfo *, BelId>> &placement) const;
// Graphics
virtual uint32_t gfxAttributes() { return 0; }
virtual void drawBel(std::vector<GraphicElement> &g, GraphicElement::style_t style, IdString bel_type, Loc loc) {};
virtual void gfxTileBel(std::vector<GraphicElement> &g, int x, int y, int z, int w, int h,
IdString bel_type, GraphicElement::style_t style) {};
virtual void drawWire(std::vector<GraphicElement> &g, GraphicElement::style_t style, Loc loc, IdString wire_type, int32_t tilewire) {};
virtual void gfxTileWire(std::vector<GraphicElement> &g, int x, int y, int w, int h, IdString wire_type,
int32_t tilewire, GraphicElement::style_t style) {};
virtual void gfxTilePip(std::vector<GraphicElement> &g, int x, int y, int w, int h, WireId src,
IdString src_type, int32_t src_id, WireId dst, IdString dst_type, int32_t dst_id,
GraphicElement::style_t style) {};
virtual void drawPip(std::vector<GraphicElement> &g,GraphicElement::style_t style, Loc loc,
WireId src, IdString src_type, int32_t src_id, WireId dst, IdString dst_type, int32_t dst_id) {};
// --- Flow hooks ---
virtual void pack() {}; // replaces the pack function

25
himbaechel/himbaechel_dbgen/chip.py
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@ -144,6 +144,7 @@ class TileWireData:
index: int
name: IdString
wire_type: IdString
tile_wire: int
const_value: IdString = field(default_factory=list)
flags: int = 0
timing_idx: int = -1
@ -166,6 +167,7 @@ class TileWireData:
def serialise(self, context: str, bba: BBAWriter):
bba.u32(self.name.index)
bba.u32(self.wire_type.index)
bba.u32(self.tile_wire)
bba.u32(self.const_value.index)
bba.u32(self.flags)
bba.u32(self.timing_idx)
@ -202,6 +204,7 @@ class PipData(BBAStruct):
@dataclass
class TileType(BBAStruct):
strs: StringPool
gfx_wire_ids: dict()
tmg: "TimingPool"
type_name: IdString
bels: list[BelData] = field(default_factory=list)
@ -229,9 +232,13 @@ class TileType(BBAStruct):
def create_wire(self, name: str, type: str="", const_value: str=""):
# Create a new tile wire of a given name and type (optional) in the tile type
tile_wire = 0
if ("TILE_WIRE_" + name) in self.gfx_wire_ids:
tile_wire = self.gfx_wire_ids["TILE_WIRE_" + name]
wire = TileWireData(index=len(self.wires),
name=self.strs.id(name),
wire_type=self.strs.id(type),
tile_wire=tile_wire,
const_value=self.strs.id(const_value))
self._wire2idx[wire.name] = wire.index
self.wires.append(wire)
@ -700,8 +707,9 @@ class Chip:
self.packages = []
self.extra_data = None
self.timing = TimingPool(self.strs)
self.gfx_wire_ids = dict()
def create_tile_type(self, name: str):
tt = TileType(self.strs, self.timing, self.strs.id(name))
tt = TileType(self.strs, self.gfx_wire_ids, self.timing, self.strs.id(name))
self.tile_type_idx[name] = len(self.tile_types)
self.tile_types.append(tt)
return tt
@ -866,3 +874,18 @@ class Chip:
bba.ref('chip_info')
self.serialise(bba)
bba.pop()
def read_gfx_h(self, filename):
with open(filename) as f:
state = 0
for line in f:
if state == 0 and line.startswith("enum GfxTileWireId"):
state = 1
elif state == 1 and line.startswith("};"):
state = 0
elif state == 1 and (line.startswith("{") or line.strip() == ""):
pass
elif state == 1:
idx = len(self.gfx_wire_ids)
name = line.strip().rstrip(",")
self.gfx_wire_ids[name] = idx

1
himbaechel/uarch/example/CMakeLists.txt
View File

@ -22,6 +22,7 @@ foreach(device ${HIMBAECHEL_EXAMPLE_DEVICES})
bbasm
${CMAKE_CURRENT_SOURCE_DIR}/example_arch_gen.py
${CMAKE_CURRENT_SOURCE_DIR}/constids.inc
${CMAKE_CURRENT_SOURCE_DIR}/gfx.h
VERBATIM)
list(APPEND chipdb_binaries ${device_bin})
endforeach()

7
himbaechel/uarch/example/constids.inc
View File

@ -18,4 +18,9 @@ X(BRAM_512X16)
X(GND)
X(GND_DRV)
X(VCC)
X(VCC_DRV)
X(VCC_DRV)
X(LUT_INPUT)
X(FF_DATA)
X(LUT_OUT)
X(FF_OUT)

83
himbaechel/uarch/example/example.cc
View File

@ -21,6 +21,7 @@
#include "log.h"
#include "nextpnr.h"
#include "util.h"
#include "gfx.h"
#include "himbaechel_helpers.h"
@ -136,10 +137,7 @@ struct ExampleImpl : HimbaechelAPI
return true;
}
uint32_t gfxAttributes() override { return GfxFlags::FLAG_INVERT_Y | GfxFlags::FLAG_SHOW_BEL; }
void gfxTileBel(std::vector<GraphicElement> &g, int x, int y, int z, int w, int h, IdString bel_type,
GraphicElement::style_t style) override
void drawBel(std::vector<GraphicElement> &g, GraphicElement::style_t style, IdString bel_type, Loc loc) override
{
GraphicElement el;
el.type = GraphicElement::TYPE_BOX;
@ -147,37 +145,98 @@ struct ExampleImpl : HimbaechelAPI
switch (bel_type.index)
{
case id_LUT4.index :
el.x1 = x + 0.15;
el.x1 = loc.x + 0.15;
el.x2 = el.x1 + 0.25;
el.y1 = y + 0.85 - (z / 2) * 0.1;
el.y1 = loc.y + 0.85 - (loc.z / 2) * 0.1;
el.y2 = el.y1 - 0.05;
g.push_back(el);
break;
case id_DFF.index :
el.x1 = x + 0.55;
el.x1 = loc.x + 0.55;
el.x2 = el.x1 + 0.25;
el.y1 = y + 0.85 - (z / 2) * 0.1;
el.y1 = loc.y + 0.85 - (loc.z / 2) * 0.1;
el.y2 = el.y1 - 0.05;
g.push_back(el);
break;
case id_GND_DRV.index :
case id_VCC_DRV.index :
case id_IOB.index :
el.x1 = x + 0.25;
el.x1 = loc.x + 0.25;
el.x2 = el.x1 + 0.50;
el.y1 = y + 0.80 - z * 0.40;
el.y1 = loc.y + 0.80 - loc.z * 0.40;
el.y2 = el.y1 - 0.25;
g.push_back(el);
break;
case id_BRAM_512X16.index :
el.x1 = x + 0.25;
el.x1 = loc.x + 0.25;
el.x2 = el.x1 + 0.50;
el.y1 = y + 0.80;
el.y1 = loc.y + 0.80;
el.y2 = el.y1 - 0.60;
g.push_back(el);
break;
}
}
void drawWire(std::vector<GraphicElement> &g, GraphicElement::style_t style, Loc loc, IdString wire_type, int32_t tilewire)
{
GraphicElement el;
el.type = GraphicElement::TYPE_LINE;
el.style = style;
int z;
switch (wire_type.index)
{
case id_LUT_INPUT.index:
z = (tilewire - TILE_WIRE_L0_I0) / 4;
el.x1 = loc.x + 0.10;
el.x2 = el.x1 + 0.05;
el.y1 = loc.y + 0.85 - z * 0.1 - ((tilewire - TILE_WIRE_L0_I0) % 4 + 1) * 0.01;
el.y2 = el.y1;
g.push_back(el);
break;
case id_LUT_OUT.index:
z = tilewire - TILE_WIRE_L0_O;
el.x1 = loc.x + 0.40;
el.x2 = el.x1 + 0.05;
el.y1 = loc.y + 0.85 - z * 0.1 - 0.025;
el.y2 = el.y1;
g.push_back(el);
break;
case id_FF_DATA.index:
z = tilewire - TILE_WIRE_L0_D;
el.x1 = loc.x + 0.50;
el.x2 = el.x1 + 0.05;
el.y1 = loc.y + 0.85 - z * 0.1 - 0.025;
el.y2 = el.y1;
g.push_back(el);
break;
case id_FF_OUT.index:
z = tilewire - TILE_WIRE_L0_Q;
el.x1 = loc.x + 0.80;
el.x2 = el.x1 + 0.05;
el.y1 = loc.y + 0.85 - z * 0.1 - 0.025;
el.y2 = el.y1;
g.push_back(el);
break;
}
}
void drawPip(std::vector<GraphicElement> &g,GraphicElement::style_t style, Loc loc,
WireId src, IdString src_type, int32_t src_id, WireId dst, IdString dst_type, int32_t dst_id)
{
GraphicElement el;
el.type = GraphicElement::TYPE_ARROW;
el.style = style;
int z;
if (src_type == id_LUT_OUT && dst_type == id_FF_DATA) {
z = src_id - TILE_WIRE_L0_O;
el.x1 = loc.x + 0.45;
el.y1 = loc.y + 0.85 - z * 0.1 - 0.025;
el.x2 = loc.x + 0.50;
el.y2 = el.y1;
g.push_back(el);
}
}
};
struct ExampleArch : HimbaechelArch

1
himbaechel/uarch/example/example_arch_gen.py
View File

@ -237,6 +237,7 @@ def main():
ch = Chip("example", "EX1", X, Y)
# Init constant ids
ch.strs.read_constids(path.join(path.dirname(__file__), "constids.inc"))
ch.read_gfx_h(path.join(path.dirname(__file__), "gfx.h"))
logic = create_logic_tiletype(ch)
io = create_io_tiletype(ch)
bram = create_bram_tiletype(ch)

101
himbaechel/uarch/example/gfx.h Normal file
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@ -0,0 +1,101 @@
/*
* nextpnr -- Next Generation Place and Route
*
* Copyright (C) 2018 gatecat <gatecat@ds0.me>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#ifndef HIMBAECHEL_EXAMPLE_GFX_H
#define HIMBAECHEL_EXAMPLE_GFX_H
#include "nextpnr.h"
NEXTPNR_NAMESPACE_BEGIN
enum GfxTileWireId
{
TILE_WIRE_NONE,
TILE_WIRE_L0_O,
TILE_WIRE_L1_O,
TILE_WIRE_L2_O,
TILE_WIRE_L3_O,
TILE_WIRE_L4_O,
TILE_WIRE_L5_O,
TILE_WIRE_L6_O,
TILE_WIRE_L7_O,
TILE_WIRE_L0_I0,
TILE_WIRE_L0_I1,
TILE_WIRE_L0_I2,
TILE_WIRE_L0_I3,
TILE_WIRE_L1_I0,
TILE_WIRE_L1_I1,
TILE_WIRE_L1_I2,
TILE_WIRE_L1_I3,
TILE_WIRE_L2_I0,
TILE_WIRE_L2_I1,
TILE_WIRE_L2_I2,
TILE_WIRE_L2_I3,
TILE_WIRE_L3_I0,
TILE_WIRE_L3_I1,
TILE_WIRE_L3_I2,
TILE_WIRE_L3_I3,
TILE_WIRE_L4_I0,
TILE_WIRE_L4_I1,
TILE_WIRE_L4_I2,
TILE_WIRE_L4_I3,
TILE_WIRE_L5_I0,
TILE_WIRE_L5_I1,
TILE_WIRE_L5_I2,
TILE_WIRE_L5_I3,
TILE_WIRE_L6_I0,
TILE_WIRE_L6_I1,
TILE_WIRE_L6_I2,
TILE_WIRE_L6_I3,
TILE_WIRE_L7_I0,
TILE_WIRE_L7_I1,
TILE_WIRE_L7_I2,
TILE_WIRE_L7_I3,
TILE_WIRE_L0_D,
TILE_WIRE_L1_D,
TILE_WIRE_L2_D,
TILE_WIRE_L3_D,
TILE_WIRE_L4_D,
TILE_WIRE_L5_D,
TILE_WIRE_L6_D,
TILE_WIRE_L7_D,
TILE_WIRE_L0_Q,
TILE_WIRE_L1_Q,
TILE_WIRE_L2_Q,
TILE_WIRE_L3_Q,
TILE_WIRE_L4_Q,
TILE_WIRE_L5_Q,
TILE_WIRE_L6_Q,
TILE_WIRE_L7_Q,
};
NEXTPNR_NAMESPACE_END
#endif