gowin: Himbaechel. Implement PLLs
- The global router is modified to work out the routing of PLL outputs and inputs; - Added API function to change wire type after its creation - there was a need to unify all wires included in the node at the stage of node creation, when all wires have already been created. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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YRabbit
myrtle
parent
6eeac1cabf
commit
49f8620ac9
@ -235,6 +235,9 @@ class TileType(BBAStruct):
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def has_wire(self, wire: str):
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# Check if a wire has already been created
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return self.strs.id(wire) in self._wire2idx
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def set_wire_type(self, wire: str, type: str):
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# wire type change
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self.wires[self._wire2idx[self.strs.id(wire)]].wire_type = self.strs.id(type)
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def serialise_lists(self, context: str, bba: BBAWriter):
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# list children of members
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for i, bel in enumerate(self.bels):
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@ -1059,6 +1059,7 @@ X(router)
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// misc
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X(GOWIN_GND)
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X(GOWIN_VCC)
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X(PLL)
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// wire types
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X(GLOBAL_CLK)
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@ -1075,6 +1076,8 @@ X(MUX_OUT)
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X(MUX_SEL)
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X(ALU_CIN)
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X(ALU_COUT)
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X(PLL_O)
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X(PLL_I)
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// fake dff inputs
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X(XD0)
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@ -43,14 +43,21 @@ struct GowinGlobalRouter
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// allow io->global, global->global and global->tile clock
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bool global_pip_filter(PipId pip) const
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{
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/*
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auto is_local = [&](IdString wire_type) {
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return !wire_type.in(id_GLOBAL_CLK, id_IO_O, id_IO_I, id_PLL_O, id_PLL_I, id_TILE_CLK);
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};
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IdString src_type = ctx->getWireType(ctx->getPipSrcWire(pip));
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IdString dst_type = ctx->getWireType(ctx->getPipDstWire(pip));
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bool src_valid = src_type.in(id_GLOBAL_CLK, id_IO_O);
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bool dst_valid = dst_type.in(id_GLOBAL_CLK, id_TILE_CLK);
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return src_valid && dst_valid;
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*/
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return true;
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bool src_valid = src_type.in(id_GLOBAL_CLK, id_IO_O, id_PLL_O);
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bool dst_valid = dst_type.in(id_GLOBAL_CLK, id_TILE_CLK, id_PLL_I, id_IO_I);
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if (ctx->debug) {
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log_info("%s <- %s [%s <- %s]\n", ctx->getWireName(ctx->getPipDstWire(pip)).str(ctx).c_str(),
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ctx->getWireName(ctx->getPipSrcWire(pip)).str(ctx).c_str(), dst_type.c_str(ctx),
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src_type.c_str(ctx));
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}
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return (src_valid && dst_valid) || (src_valid && is_local(dst_type)) || (is_local(src_type) && dst_valid);
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}
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bool is_relaxed_sink(const PortRef &sink) const { return false; }
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@ -151,10 +158,19 @@ struct GowinGlobalRouter
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void route_clk_net(NetInfo *net)
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{
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for (auto usr : net->users.enumerate())
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backwards_bfs_route(net, usr.index, 1000000, true,
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[&](PipId pip) { return (is_relaxed_sink(usr.value) || global_pip_filter(pip)); });
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log_info(" routed net '%s' using global resources\n", ctx->nameOf(net));
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bool routed = false;
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for (auto usr : net->users.enumerate()) {
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routed = backwards_bfs_route(net, usr.index, 1000000, true, [&](PipId pip) {
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return (is_relaxed_sink(usr.value) || global_pip_filter(pip));
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});
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if (!routed) {
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break;
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}
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}
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if (routed) {
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log_info(" routed net '%s' using global resources\n", ctx->nameOf(net));
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}
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}
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bool driver_is_clksrc(const PortRef &driver)
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@ -166,10 +182,24 @@ struct GowinGlobalRouter
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IdStringList pin_func = gwu.get_pin_funcs(driver.cell->bel);
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for (size_t i = 0; i < pin_func.size(); ++i) {
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if (pin_func[i].str(ctx).rfind("GCLKT", 0) == 0) {
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if (ctx->debug) {
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log_info("Clock pin:%s:%s\n", ctx->getBelName(driver.cell->bel).str(ctx).c_str(),
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pin_func[i].c_str(ctx));
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}
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return true;
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}
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}
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}
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// PLL outputs
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if (driver.cell->type.in(id_rPLL, id_PLLVR)) {
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if (driver.port.in(id_CLKOUT, id_CLKOUTD, id_CLKOUTD3, id_CLKOUTP)) {
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if (ctx->debug) {
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log_info("PLL out:%s:%s\n", ctx->getBelName(driver.cell->bel).str(ctx).c_str(),
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driver.port.c_str(ctx));
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}
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return true;
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}
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}
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return false;
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}
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@ -39,6 +39,8 @@ enum
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ALU0_Z = 30, // :35, 6 ALU
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RAMW_Z = 36, // RAM16SDP4
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PLL_Z = 275,
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GSR_Z = 276,
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VCC_Z = 277,
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VSS_Z = 278
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};
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@ -22,6 +22,7 @@ MUX27_Z = 29
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ALU0_Z = 30 # : 35, 6 ALUs
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RAMW_Z = 36 # RAM16SDP4
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PLL_Z = 275
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GSR_Z = 276
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VCC_Z = 277
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GND_Z = 278
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@ -121,8 +122,11 @@ def create_nodes(chip: Chip, db: chipdb):
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global_nodes.setdefault('VCC', []).append(NodeWire(x, y, 'VCC'))
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# add nodes from the apicula db
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for node_name, node in db.nodes.items():
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for node_name, node_hdr in db.nodes.items():
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wire_type, node = node_hdr
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for y, x, wire in node:
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if wire_type:
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chip.tile_type_at(x, y).set_wire_type(wire, wire_type)
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new_node = NodeWire(x, y, wire)
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gl_nodes = global_nodes.setdefault(node_name, [])
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if new_node not in gl_nodes:
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@ -139,9 +143,7 @@ def create_nodes(chip: Chip, db: chipdb):
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# coordinates.
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def create_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
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def get_wire_type(name):
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if name.startswith('GB') or name.startswith('GT'):
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return "GLOBAL_CLK"
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elif name in {'XD0', 'XD1', 'XD2', 'XD3', 'XD4', 'XD5',}:
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if name in {'XD0', 'XD1', 'XD2', 'XD3', 'XD4', 'XD5',}:
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return "X0"
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return ""
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@ -150,7 +152,7 @@ def create_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
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tt.create_wire(dst, get_wire_type(dst))
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for src in srcs.keys():
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if not tt.has_wire(src):
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tt.create_wire(src, get_wire_type(dst))
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tt.create_wire(src, get_wire_type(src))
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tt.create_pip(src, dst)
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# clock wires
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for dst, srcs in db.grid[y][x].clock_pips.items():
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@ -336,18 +338,56 @@ def create_ssram_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
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for i in range(4):
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tt.add_bel_pin(ff, f"DI[{i}]", f"{lut_inputs[i]}5", PinType.INPUT)
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tt.add_bel_pin(ff, f"WAD[{i}]", f"{lut_inputs[i]}4", PinType.INPUT)
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# RAD[0] is RAD[0] is assumed to be connected to A3, A2, A1 and A0. But
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# RAD[0] is assumed to be connected to A3, A2, A1 and A0. But
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# for now we connect it only to A0, the others will be connected
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# directly during packing. RAD[1...3] - similarly.
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tt.add_bel_pin(ff, f"RAD[{i}]", f"{lut_inputs[i]}0", PinType.INPUT)
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tt.add_bel_pin(ff, f"DO[{i}]", f"F{i}", PinType.OUTPUT)
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tt.add_bel_pin(ff, f"CLK", "CLK2", PinType.INPUT)
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tt.add_bel_pin(ff, f"CE", "CE2", PinType.INPUT)
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tt.add_bel_pin(ff, f"WRE", "LSR2", PinType.INPUT)
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return (ttyp, tt)
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# PLL main tile
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_pll_inputs = {'CLKFB', 'FBDSEL0', 'FBDSEL1', 'FBDSEL2', 'FBDSEL3',
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'FBDSEL4', 'FBDSEL5', 'IDSEL0', 'IDSEL1', 'IDSEL2', 'IDSEL3',
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'IDSEL4', 'IDSEL5', 'ODSEL0', 'ODSEL1', 'ODSEL2', 'ODSEL3',
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'ODSEL4', 'ODSEL5', 'RESET', 'RESET_P', 'PSDA0', 'PSDA1',
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'PSDA2', 'PSDA3', 'DUTYDA0', 'DUTYDA1', 'DUTYDA2', 'DUTYDA3',
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'FDLY0', 'FDLY1', 'FDLY2', 'FDLY3', 'CLKIN'}
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_pll_outputs = {'CLKOUT', 'LOCK', 'CLKOUTP', 'CLKOUTD', 'CLKOUTD3'}
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def create_pll_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
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if ttyp in created_tiletypes:
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return ttyp, None
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typename = "PLL"
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tt = chip.create_tile_type(f"{typename}_{ttyp}")
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tt.extra_data = TileExtraData(chip.strs.id(typename))
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# wires
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if chip.name == 'GW1NS-4':
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pll_name = 'PLLVR'
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bel_type = 'PLLVR'
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else:
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pll_name = 'RPLLA'
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bel_type = 'rPLL'
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portmap = db.grid[y][x].bels[pll_name].portmap
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pll = tt.create_bel("PLL", bel_type, z = PLL_Z)
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# Not sure how this will affect routing - PLLs are fixed and their outputs
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# will be handled by a dedicated router
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#pll.flags = BEL_FLAG_GLOBAL
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for pin, wire in portmap.items():
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if pin in _pll_inputs:
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tt.create_wire(wire, "PLL_I")
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tt.add_bel_pin(pll, pin, wire, PinType.INPUT)
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else:
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assert pin in _pll_outputs, f"Unknown PLL pin{pin}"
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tt.create_wire(wire, "PLL_O")
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tt.add_bel_pin(pll, pin, wire, PinType.OUTPUT)
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create_switch_matrix(tt, db, x, y)
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return (ttyp, tt)
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# pinouts, packages...
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_tbrlre = re.compile(r"IO([TBRL])(\d+)(\w)")
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def create_packages(chip: Chip, db: chipdb):
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@ -411,9 +451,10 @@ def main():
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# these differences (in case it turns out later that there is a slightly
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# different routing or something like that).
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logic_tiletypes = {12, 13, 14, 15, 16}
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io_tiletypes = {52, 53, 55, 58, 59, 64, 65, 66}
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io_tiletypes = {52, 53, 54, 55, 58, 59, 64, 65, 66}
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ssram_tiletypes = {17, 18, 19}
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gsr_tiletypes = {1}
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pll_tiletypes = {86, 87, 42, 45}
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# Setup tile grid
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for x in range(X):
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for y in range(Y):
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@ -440,6 +481,10 @@ def main():
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ttyp, _ = create_io_tiletype(ch, db, x, y, ttyp)
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created_tiletypes.add(ttyp)
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ch.set_tile_type(x, y, f"IO_{ttyp}")
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elif ttyp in pll_tiletypes:
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ttyp, _ = create_pll_tiletype(ch, db, x, y, ttyp)
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created_tiletypes.add(ttyp)
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ch.set_tile_type(x, y, f"PLL_{ttyp}")
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else:
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ttyp, _ = create_null_tiletype(ch, db, x, y, ttyp)
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created_tiletypes.add(ttyp)
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@ -505,17 +505,18 @@ struct GowinPacker
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}
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}
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// Pack global set-reset
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// ===================================
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// Global set/reset
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// ===================================
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void pack_gsr(void)
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{
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log_info("Packing GSR..\n");
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bool user_gsr = false;
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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if (ctx->verbose)
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log_info("cell '%s' is of type '%s'\n", ctx->nameOf(ci), ci->type.c_str(ctx));
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if (ci->type == id_GSR) {
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auto &ci = *cell.second;
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if (ci.type == id_GSR) {
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user_gsr = true;
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break;
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}
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@ -541,6 +542,32 @@ struct GowinPacker
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}
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}
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// ===================================
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// PLL
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// ===================================
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void pack_pll(void)
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{
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log_info("Packing PLL..\n");
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for (auto &cell : ctx->cells) {
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auto &ci = *cell.second;
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if (ci.type == id_rPLL) {
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// pin renaming for compatibility
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for (int i = 0; i < 6; ++i) {
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ci.renamePort(ctx->idf("FBDSEL[%d]", i), ctx->idf("FBDSEL%d", i));
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ci.renamePort(ctx->idf("IDSEL[%d]", i), ctx->idf("IDSEL%d", i));
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ci.renamePort(ctx->idf("ODSEL[%d]", i), ctx->idf("ODSEL%d", i));
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if (i < 4) {
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ci.renamePort(ctx->idf("PSDA[%d]", i), ctx->idf("PSDA%d", i));
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ci.renamePort(ctx->idf("DUTYDA[%d]", i), ctx->idf("DUTYDA%d", i));
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ci.renamePort(ctx->idf("FDLY[%d]", i), ctx->idf("FDLY%d", i));
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}
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}
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}
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}
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}
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void run(void)
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{
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pack_iobs();
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@ -549,6 +576,7 @@ struct GowinPacker
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pack_wideluts();
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pack_alus();
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constrain_lutffs();
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pack_pll();
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pack_ram16sdp4();
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}
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};
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