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run clangformat

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2023-12-26 09:54:34 +01:00
parent 41914876ef
commit 4a4025192a
7 changed files with 15 additions and 12 deletions
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2
common/kernel/pybindings.cc
View File

@ -305,7 +305,7 @@ void (*python_sighandler)(int) = nullptr;
void init_python(const char *executable)
{
#ifdef MAIN_EXECUTABLE
static const char* python_argv[1];
static const char *python_argv[1];
python_argv[0] = executable;
py::initialize_interpreter(true, 1, python_argv);
py::module::import(TOSTRING(MODULE_NAME));

6
common/route/router2.cc
View File

@ -781,8 +781,10 @@ struct Router2
WireScore next_score;
next_score.delay = curr.score.delay + cfg.get_base_cost(ctx, next, uh, crit_weight);
next_score.cost = curr.score.cost + score_wire_for_arc(net, i, phys_pin, next, uh, crit_weight);
next_score.togo_cost =
const_mode ? 0 : cfg.estimate_weight * get_togo_cost(net, i, next_idx, src_wire, true, crit_weight);
next_score.togo_cost = const_mode
? 0
: cfg.estimate_weight * get_togo_cost(net, i, next_idx, src_wire,
true, crit_weight);
if (was_visited_bwd(next_idx, next_score.delay)) {
// Don't expand the same node twice.
continue;

3
ecp5/pack.cc
View File

@ -240,7 +240,8 @@ class Ecp5Packer
ci->disconnectPort(id_M);
ci->ports.erase(id_M);
}
if (di && di->driver.cell != nullptr && di->driver.cell->type == id_TRELLIS_COMB && di->driver.port == id_F) {
if (di && di->driver.cell != nullptr && di->driver.cell->type == id_TRELLIS_COMB &&
di->driver.port == id_F) {
CellInfo *comb = di->driver.cell;
if (comb->cluster != ClusterId()) {
// Special procedure where the comb cell is part of an existing macro

6
gowin/pack.cc
View File

@ -19,9 +19,9 @@
*/
#include <algorithm>
#include <cinttypes>
#include <iostream>
#include <iterator>
#include <cinttypes>
#include "cells.h"
#include "design_utils.h"
#include "log.h"
@ -673,8 +673,8 @@ static void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constne
uc_init &= (1LL << uc_init_len) - 1;
if (ctx->verbose)
log_info("%s lut config modified from 0x%" PRIX64 " to 0x%" PRIX64 "\n", ctx->nameOf(uc), it_param->second.intval,
uc_init);
log_info("%s lut config modified from 0x%" PRIX64 " to 0x%" PRIX64 "\n", ctx->nameOf(uc),
it_param->second.intval, uc_init);
it_param->second = Property(uc_init, uc_init_len);
uc->ports[user.port].net = nullptr;

4
gui/fpgaviewwidget.cc
View File

@ -574,8 +574,8 @@ void FPGAViewWidget::renderLines(void)
}
rendererData_->bbGlobal.setX0(-1.0f);
rendererData_->bbGlobal.setY0(-1.0f);
rendererData_->bbGlobal.setX1(1.0f * (ctx_->getGridDimX()+1));
rendererData_->bbGlobal.setY1(1.0f * (ctx_->getGridDimY()+1));
rendererData_->bbGlobal.setX1(1.0f * (ctx_->getGridDimX() + 1));
rendererData_->bbGlobal.setY1(1.0f * (ctx_->getGridDimY() + 1));
rendererData_->gfxGrid.last_render++;
}
if (highlightedOrSelectedChanged) {

2
ice40/arch.cc
View File

@ -674,7 +674,7 @@ bool Arch::place()
{
cfg.cell_groups.emplace_back();
auto& comb = cfg.cell_groups.back();
auto &comb = cfg.cell_groups.back();
comb.name = getCtx()->id("DSP");
comb.cell_area[id_ICESTORM_DSP] = StaticRect(0.9f, 5.0f);
comb.bel_area[id_ICESTORM_DSP] = StaticRect(0.9f, 5.0f);

4
nexus/pack.cc
View File

@ -1321,8 +1321,8 @@ struct NexusPacker
NetInfo *cin = ci->getPort(id_CIN);
if (cin) {
if (cin->driver.cell && cin->driver.cell->type != id_CCU2) {
log_error("CCU2 '%s' CIN net '%s' driven by non-CCU2 cell '%s'.\n",
ctx->nameOf(ci), ctx->nameOf(cin), ctx->nameOf(cin->driver.cell));
log_error("CCU2 '%s' CIN net '%s' driven by non-CCU2 cell '%s'.\n", ctx->nameOf(ci),
ctx->nameOf(cin), ctx->nameOf(cin->driver.cell));
}
continue;
}