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Start adding data for placement constraint solving.

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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2021-02-01 14:26:57 -08:00
parent 5c16c5024d
commit 4a62c8c2eb
2 changed files with 43 additions and 50 deletions
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66
fpga_interchange/arch.cc
View File

@ -164,18 +164,17 @@ WireId Arch::getBelPinWire(BelId bel, IdString pin) const
NPNR_ASSERT(bel != BelId());
int pin_index = getBelPinIndex(bel, pin);
if(pin_index < 0) {
// Port could not be found!
auto &bel_data = locInfo(bel).bel_data[bel.index];
NPNR_ASSERT(pin_index >= 0 && pin_index < bel_data.num_bel_wires);
const int32_t *wires = bel_data.wires.get();
int32_t wire_index = wires[pin_index];
if(wire_index < 0) {
// This BEL pin is not connected.
return WireId();
} else {
const int32_t *wires = locInfo(bel).bel_data[bel.index].wires.get();
int32_t wire_index = wires[pin_index];
if(wire_index < 0) {
// This BEL pin is not connected.
return WireId();
} else {
return canonicalWireId(chip_info, bel.tile, wire_index);
}
return canonicalWireId(chip_info, bel.tile, wire_index);
}
}
@ -429,23 +428,6 @@ std::vector<std::pair<IdString, std::string>> Arch::getPipAttrs(PipId pip) const
// -----------------------------------------------------------------------
std::vector<IdString> Arch::getBelPins(BelId bel) const
{
std::vector<IdString> ret;
NPNR_ASSERT(bel != BelId());
// FIXME: The std::vector here can be replaced by a int32_t -> IdString
// range wrapper.
int num_bel_wires = locInfo(bel).bel_data[bel.index].num_bel_wires;
const int32_t *ports = locInfo(bel).bel_data[bel.index].ports.get();
for (int i = 0; i < num_bel_wires; i++) {
ret.push_back(IdString(ports[i]));
}
return ret;
}
BelId Arch::getBelByLocation(Loc loc) const
{
BelId bi;
@ -466,12 +448,6 @@ std::vector<std::pair<IdString, std::string>> Arch::getBelAttrs(BelId bel) const
// -----------------------------------------------------------------------
delay_t Arch::estimateDelay(WireId src, WireId dst, bool debug) const
{
// FIXME: Implement something to push the A* router in the right direction.
return 0;
}
ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
{
int dst_tile = dst.tile == -1 ? chip_info->nodes[dst.index].tile_wires[0].tile : dst.tile;
@ -501,23 +477,11 @@ ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
return {x0, y0, x1, y1};
}
delay_t Arch::getBoundingBoxCost(WireId src, WireId dst, int distance) const
{
// FIXME: Implement when adding timing-driven place and route.
return 0;
}
delay_t Arch::getWireRipupDelayPenalty(WireId wire) const
{
return getRipupDelayPenalty();
}
delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
{
// FIXME: Implement when adding timing-driven place and route.
return 0;
}
bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; }
// -----------------------------------------------------------------------
@ -565,6 +529,18 @@ DecalXY Arch::getGroupDecal(GroupId pip) const { return {}; };
// -----------------------------------------------------------------------
delay_t Arch::estimateDelay(WireId src, WireId dst, bool debug) const
{
// FIXME: Implement something to push the A* router in the right direction.
return 0;
}
delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
{
// FIXME: Implement when adding timing-driven place and route.
return 0;
}
bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
{
// FIXME: Implement when adding timing-driven place and route.

27
fpga_interchange/arch.h
View File

@ -29,6 +29,8 @@
NEXTPNR_NAMESPACE_BEGIN
#include "fpga_interchange_generated_defs.h"
/**** Everything in this section must be kept in sync with chipdb.py ****/
template <typename T> struct RelPtr
@ -713,10 +715,11 @@ struct Arch : BaseCtx
struct TileStatus
{
std::bitset<kMaxNumberOfCells> bel_available;
std::vector<CellInfo *> boundcells;
};
std::vector<TileStatus> tileStatus;
std::unordered_map<TileStatus> tileStatus;
ArchArgs args;
Arch(ArchArgs args);
@ -836,7 +839,7 @@ struct Arch : BaseCtx
bool getBelGlobalBuf(BelId bel) const
{
// TODO: This probably needs to be fixed!
// FIXME: This probably needs to be fixed!
return false;
}
@ -867,7 +870,20 @@ struct Arch : BaseCtx
WireId getBelPinWire(BelId bel, IdString pin) const;
PortType getBelPinType(BelId bel, IdString pin) const;
std::vector<IdString> getBelPins(BelId bel) const;
IdStringRange getBelPins(BelId bel) const
{
NPNR_ASSERT(bel != BelId());
int num_bel_wires = locInfo(bel).bel_data[bel.index].num_bel_wires;
const int32_t *ports = locInfo(bel).bel_data[bel.index].ports.get();
IdStringRange str_range;
str_range.b.cursor = &ports[0];
str_range.b.cursor = &ports[num_bel_wires-1];
return str_range;
}
bool isBelLocked(BelId bel) const;
@ -1168,7 +1184,7 @@ struct Arch : BaseCtx
// -------------------------------------------------
// TODO: Use groups to get access to sites.
// FIXME: Use groups to get access to sites.
GroupId getGroupByName(IdString name) const { return GroupId(); }
IdString getGroupName(GroupId group) const { return IdString(); }
std::vector<GroupId> getGroups() const { return {}; }
@ -1181,7 +1197,6 @@ struct Arch : BaseCtx
delay_t estimateDelay(WireId src, WireId dst, bool debug = false) const;
delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const;
ArcBounds getRouteBoundingBox(WireId src, WireId dst) const;
delay_t getBoundingBoxCost(WireId src, WireId dst, int distance) const;
delay_t getDelayEpsilon() const { return 20; }
delay_t getRipupDelayPenalty() const { return 120; }
delay_t getWireRipupDelayPenalty(WireId wire) const;
@ -1292,6 +1307,8 @@ struct Arch : BaseCtx
// This is not intended for Bel type checks, but finer-grained constraints
// such as conflicting set/reset signals, etc
bool isValidBelForCell(CellInfo *cell, BelId bel) const {
NPNR_ASSERT(isValidBelForCellType(cell->type, bel));
// FIXME: Implement this
return true;
}