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Fix ice40 pip/switch locked performance issue

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-06-10 14:08:00 +02:00
parent 8d5da98122
commit 4a79e70470
3 changed files with 9 additions and 16 deletions
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2
ice40/chip.cc
View File

@ -97,7 +97,7 @@ Chip::Chip(ChipArgs args) : args(args)
bel_to_cell.resize(chip_info.num_bels); bel_to_cell.resize(chip_info.num_bels);
wire_to_net.resize(chip_info.num_wires); wire_to_net.resize(chip_info.num_wires);
pip_to_net.resize(chip_info.num_pips); pip_to_net.resize(chip_info.num_pips);
pips_locked.resize(chip_info.num_pips); switches_locked.resize(chip_info.num_switches);
} }
// ----------------------------------------------------------------------- // -----------------------------------------------------------------------

21
ice40/chip.h
View File

@ -162,6 +162,7 @@ struct ChipInfoPOD
{ {
int width, height; int width, height;
int num_bels, num_wires, num_pips; int num_bels, num_wires, num_pips;
int num_switches;
BelInfoPOD *bel_data; BelInfoPOD *bel_data;
WireInfoPOD *wire_data; WireInfoPOD *wire_data;
PipInfoPOD *pip_data; PipInfoPOD *pip_data;
@ -411,7 +412,7 @@ struct Chip
vector<IdString> bel_to_cell; vector<IdString> bel_to_cell;
vector<IdString> wire_to_net; vector<IdString> wire_to_net;
vector<IdString> pip_to_net; vector<IdString> pip_to_net;
vector<bool> pips_locked; vector<bool> switches_locked;
Chip(ChipArgs args); Chip(ChipArgs args);
ChipArgs args; ChipArgs args;
@ -567,32 +568,24 @@ struct Chip
{ {
assert(pip != PipId()); assert(pip != PipId());
assert(pip_to_net[pip.index] == IdString()); assert(pip_to_net[pip.index] == IdString());
assert(!switches_locked[chip_info.pip_data[pip.index].switch_index]);
pip_to_net[pip.index] = net; pip_to_net[pip.index] = net;
// Optimise? switches_locked[chip_info.pip_data[pip.index].switch_index] = true;
for (int i = 0; i < chip_info.num_pips; i++) {
if (chip_info.pip_data[i].switch_index ==
chip_info.pip_data[pip.index].switch_index)
pips_locked[i] = true;
}
} }
void unbindPip(PipId pip) void unbindPip(PipId pip)
{ {
assert(pip != PipId()); assert(pip != PipId());
assert(pip_to_net[pip.index] != IdString()); assert(pip_to_net[pip.index] != IdString());
assert(switches_locked[chip_info.pip_data[pip.index].switch_index]);
pip_to_net[pip.index] = IdString(); pip_to_net[pip.index] = IdString();
// Optimise? switches_locked[chip_info.pip_data[pip.index].switch_index] = false;
for (int i = 0; i < chip_info.num_pips; i++) {
if (chip_info.pip_data[i].switch_index ==
chip_info.pip_data[pip.index].switch_index)
pips_locked[i] = false;
}
} }
bool checkPipAvail(PipId pip) const bool checkPipAvail(PipId pip) const
{ {
assert(pip != PipId()); assert(pip != PipId());
return !pips_locked[pip.index]; return !switches_locked[chip_info.pip_data[pip.index].switch_index];
} }
IdString getPipNet(PipId pip) const IdString getPipNet(PipId pip) const

2
ice40/chipdb.py
View File

@ -451,7 +451,7 @@ print(",\n".join(tilegrid))
print("};") print("};")
print("ChipInfoPOD chip_info_%s = {" % dev_name) print("ChipInfoPOD chip_info_%s = {" % dev_name)
print(" %d, %d, %d, %d, %d," % (dev_width, dev_height, len(bel_name), num_wires, len(pipinfo))) print(" %d, %d, %d, %d, %d, %d," % (dev_width, dev_height, len(bel_name), num_wires, len(pipinfo), len(switchinfo)))
print(" bel_data_%s, wire_data_%s, pip_data_%s," % (dev_name, dev_name, dev_name)) print(" bel_data_%s, wire_data_%s, pip_data_%s," % (dev_name, dev_name, dev_name))
print(" tile_grid_%s, &bits_info_%s" % (dev_name, dev_name)) print(" tile_grid_%s, &bits_info_%s" % (dev_name, dev_name))
print("};") print("};")