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Add getBelPinType to Python interface.

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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2021-03-19 17:18:01 -07:00
parent 53ed6979a9
commit 4cd74bba2c
3 changed files with 10 additions and 0 deletions
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2
common/arch_pybindings_shared.h
View File

@ -60,6 +60,8 @@ fn_wrapper_0a<Context, decltype(&Context::getBels), &Context::getBels, wrap_cont
fn_wrapper_2a<Context, decltype(&Context::getBelPinWire), &Context::getBelPinWire, conv_to_str<WireId>,
conv_from_str<BelId>, conv_from_str<IdString>>::def_wrap(ctx_cls, "getBelPinWire");
fn_wrapper_2a<Context, decltype(&Context::getBelPinType), &Context::getBelPinType, pass_through<PortType>,
conv_from_str<BelId>, conv_from_str<IdString>>::def_wrap(ctx_cls, "getBelPinType");
fn_wrapper_1a<Context, decltype(&Context::getWireBelPins), &Context::getWireBelPins, wrap_context<BelPinRange>,
conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireBelPins");

4
fpga_interchange/examples/devices/xc7a35t/test_data.yaml
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@ -34,3 +34,7 @@ bel_pin_test:
- bel: $CONSTANTS_X0Y0.$CONSTANTS/VCC
pin: P
wire: $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
- bel: SLICE_X1Y19.SLICEL/SRUSEDGND
pin: "0"
wire: SLICE_X1Y19.SLICEL/SRUSEDGND_HARD0
type: PORT_OUT

4
python/check_arch_api.py
View File

@ -78,6 +78,10 @@ def check_arch_api(ctx):
wire_name = ctx.getBelPinWire(bel_pin_test['bel'], bel_pin_test['pin'])
assert bel_pin_test['wire'] == wire_name, (bel_pin_test['wire'], wire_name)
if 'type' in bel_pin_test:
pin_type = ctx.getBelPinType(bel_pin_test['bel'], bel_pin_test['pin'])
assert bel_pin_test['type'] == pin_type.name, (bel_pin_test['type'], pin_type)
bel_pins_tested += 1
print('Tested {} pips and {} bel pins'.format(pips_tested, bel_pins_tested))