Merge remote-tracking branch 'origin/master' into chipdbng

common/design_utils.h

@@ -72,7 +72,7 @@ CellInfo *net_only_drives(NetInfo *net, F1 cell_pred, IdString port,
 // If a net is driven by a given port of a cell matching a predicate, return
 // that cell, otherwise nullptr
 template <typename F1>
-CellInfo *net_driven_by(NetInfo *net, F1 cell_pred, IdString port)
+CellInfo *net_driven_by(const NetInfo *net, F1 cell_pred, IdString port)
 {
     if (net == nullptr)
         return nullptr;

common/place.cc

@@ -17,31 +17,243 @@
  *
  */
 
+#include "place.h"
+#include <algorithm>
+#include <cmath>
 #include <iostream>
+#include <limits>
 #include <list>
 #include <map>
 #include <ostream>
+#include <queue>
+#include <random>
 #include <set>
 #include <stdarg.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
 #include <vector>
-
 #include "arch_place.h"
 #include "log.h"
-#include "place.h"
 
 NEXTPNR_NAMESPACE_BEGIN
 
-void place_design(Design *design)
+struct rnd_state
 {
-    std::set<IdString> types_used;
-    std::set<IdString>::iterator not_found, element;
-    std::set<BelType> used_bels;
+    uint32_t state;
+};
 
-    log_info("Placing..\n");
+/* The state word must be initialized to non-zero */
+static uint32_t xorshift32(rnd_state &rnd)
+{
+    /* Algorithm "xor" from p. 4 of Marsaglia, "Xorshift RNGs" */
+    uint32_t x = rnd.state;
+    x ^= x << 13;
+    x ^= x >> 17;
+    x ^= x << 5;
+    rnd.state = x;
+    return x;
+}
 
+static float random_float_upto(rnd_state &rnd, float limit)
+{
+    return xorshift32(rnd) / (4294967296 / limit);
+}
+
+static int random_int_between(rnd_state &rnd, int a, int b)
+{
+    return a + int(random_float_upto(rnd, b - a));
+}
+
+// Initial random placement
+static void place_initial(Design *design, CellInfo *cell, rnd_state &rnd)
+{
+    BelId best_bel = BelId();
+    float best_score = std::numeric_limits<float>::infinity();
+    Chip &chip = design->chip;
+    if (cell->bel != BelId()) {
+        chip.unbindBel(cell->bel);
+        cell->bel = BelId();
+    }
+    BelType targetType = belTypeFromId(cell->type);
+    for (auto bel : chip.getBels()) {
+        if (chip.getBelType(bel) == targetType && chip.checkBelAvail(bel) &&
+            isValidBelForCell(design, cell, bel)) {
+            float score = random_float_upto(rnd, 1.0);
+            if (score <= best_score) {
+                best_score = score;
+                best_bel = bel;
+            }
+        }
+    }
+    if (best_bel == BelId()) {
+        log_error("failed to place cell '%s' of type '%s'\n",
+                  cell->name.c_str(), cell->type.c_str());
+    }
+    cell->bel = best_bel;
+    chip.bindBel(cell->bel, cell->name);
+
+    // Back annotate location
+    cell->attrs["BEL"] = chip.getBelName(cell->bel).str();
+}
+
+// Stores the state of the SA placer
+struct SAState
+{
+    std::unordered_map<NetInfo *, float> wirelengths;
+    float curr_wirelength = std::numeric_limits<float>::infinity();
+    float temp = 1000;
+    bool improved = false;
+    int n_move, n_accept;
+    int diameter = 35;
+    std::vector<std::vector<std::vector<std::vector<BelId>>>> fast_bels;
+};
+
+// Get the total estimated wirelength for a net
+static float get_wirelength(Chip *chip, NetInfo *net)
+{
+    float wirelength = 0;
+    float driver_x = 0, driver_y = 0;
+    bool consider_driver = false;
+    CellInfo *driver_cell = net->driver.cell;
+    if (!driver_cell)
+        return 0;
+    if (driver_cell->bel == BelId())
+        return 0;
+    consider_driver =
+            chip->estimatePosition(driver_cell->bel, driver_x, driver_y);
+    if (!consider_driver)
+        return 0;
+    for (auto load : net->users) {
+        if (load.cell == nullptr)
+            continue;
+        CellInfo *load_cell = load.cell;
+        float load_x = 0, load_y = 0;
+        if (load_cell->bel == BelId())
+            continue;
+        chip->estimatePosition(load_cell->bel, load_x, load_y);
+        wirelength += std::abs(load_x - driver_x) + std::abs(load_y - driver_y);
+    }
+    return wirelength;
+}
+
+// Attempt a SA position swap, return true on success or false on failure
+static bool try_swap_position(Design *design, CellInfo *cell, BelId newBel,
+                              rnd_state &rnd, SAState &state)
+{
+    static std::unordered_set<NetInfo *> update;
+    static std::vector<std::pair<NetInfo *, float>> new_lengths;
+    new_lengths.clear();
+    update.clear();
+    Chip &chip = design->chip;
+    BelId oldBel = cell->bel;
+    IdString other = chip.getBelCell(newBel, true);
+    CellInfo *other_cell = nullptr;
+    float new_wirelength = 0, delta;
+    chip.unbindBel(oldBel);
+    if (other != IdString()) {
+        other_cell = design->cells[other];
+        chip.unbindBel(newBel);
+    }
+    if (!isValidBelForCell(design, cell, newBel))
+        goto swap_fail;
+
+    for (const auto &port : cell->ports)
+        if (port.second.net != nullptr)
+            update.insert(port.second.net);
+
+    if (other != IdString()) {
+        if (!isValidBelForCell(design, other_cell, oldBel))
+            goto swap_fail;
+        for (const auto &port : other_cell->ports)
+            if (port.second.net != nullptr)
+                update.insert(port.second.net);
+    }
+
+    chip.bindBel(newBel, cell->name);
+    if (other != IdString()) {
+        if (!isValidBelForCell(design, other_cell, oldBel)) {
+            chip.unbindBel(newBel);
+            goto swap_fail;
+        } else {
+            chip.bindBel(oldBel, other_cell->name);
+        }
+    }
+
+    cell->bel = newBel;
+    if (other != IdString())
+        other_cell->bel = oldBel;
+
+    new_wirelength = state.curr_wirelength;
+
+    // Recalculate wirelengths for all nets touched by the peturbation
+    for (auto net : update) {
+        new_wirelength -= state.wirelengths.at(net);
+        float net_new_wl = get_wirelength(&chip, net);
+        new_wirelength += net_new_wl;
+        new_lengths.push_back(std::make_pair(net, net_new_wl));
+    }
+    delta = new_wirelength - state.curr_wirelength;
+    state.n_move++;
+    // SA acceptance criterea
+    if (delta < 0 ||
+        (state.temp > 1e-6 &&
+         random_float_upto(rnd, 1.0) <= std::exp(-delta / state.temp))) {
+        state.n_accept++;
+        if (delta < 0)
+            state.improved = true;
+    } else {
+        if (other != IdString())
+            chip.unbindBel(oldBel);
+        chip.unbindBel(newBel);
+        goto swap_fail;
+    }
+    state.curr_wirelength = new_wirelength;
+    for (auto new_wl : new_lengths)
+        state.wirelengths.at(new_wl.first) = new_wl.second;
+
+    return true;
+swap_fail:
+    chip.bindBel(oldBel, cell->name);
+    cell->bel = oldBel;
+    if (other != IdString()) {
+        chip.bindBel(newBel, other);
+        other_cell->bel = newBel;
+    }
+    return false;
+}
+
+// Find a random Bel of the correct type for a cell, within the specified
+// diameter
+BelId random_bel_for_cell(Design *design, CellInfo *cell, SAState &state,
+                          rnd_state &rnd)
+{
+    BelId best_bel = BelId();
+    Chip &chip = design->chip;
+    BelType targetType = belTypeFromId(cell->type);
+    assert(int(targetType) < state.fast_bels.size());
+    float x = 0, y = 0;
+    chip.estimatePosition(cell->bel, x, y);
+    while (true) {
+        int nx = random_int_between(rnd, std::max(int(x) - state.diameter, 0),
+                                    int(x) + state.diameter + 1);
+        int ny = random_int_between(rnd, std::max(int(y) - state.diameter, 0),
+                                    int(y) + state.diameter + 1);
+        if (nx >= state.fast_bels.at(int(targetType)).size())
+            continue;
+        if (ny >= state.fast_bels.at(int(targetType)).at(nx).size())
+            continue;
+        const auto &fb = state.fast_bels.at(int(targetType)).at(nx).at(ny);
+        if (fb.size() == 0)
+            continue;
+        return fb.at(random_int_between(rnd, 0, fb.size()));
+    }
+}
+
+void place_design_sa(Design *design)
+{
+    size_t total_cells = design->cells.size(), placed_cells = 0;
+    std::queue<CellInfo *> visit_cells;
     // Initial constraints placer
     for (auto cell_entry : design->cells) {
         CellInfo *cell = cell_entry.second;
@@ -65,59 +277,109 @@ void place_design(Design *design)
 
             cell->bel = bel;
             design->chip.bindBel(bel, cell->name);
+            placed_cells++;
+            visit_cells.push(cell);
         }
     }
-
-    for (auto cell_entry : design->cells) {
-        CellInfo *cell = cell_entry.second;
-        // Ignore already placed cells
-        if (cell->bel != BelId())
-            continue;
-
-        BelType bel_type;
-
-        element = types_used.find(cell->type);
-        if (element != types_used.end()) {
-            continue;
+    log_info("place_constraints placed %d\n", placed_cells);
+    rnd_state rnd;
+    rnd.state = 1;
+    std::vector<CellInfo *> autoplaced;
+    SAState state;
+    // Place cells randomly initially
+    for (auto cell : design->cells) {
+        CellInfo *ci = cell.second;
+        if (ci->bel == BelId()) {
+            place_initial(design, ci, rnd);
+            autoplaced.push_back(cell.second);
+            placed_cells++;
         }
-
-        bel_type = belTypeFromId(cell->type);
-        if (bel_type == BelType()) {
-            log_error("No Bel of type \'%s\' defined for "
-                      "this chip\n",
-                      cell->type.c_str());
-        }
-        types_used.insert(cell->type);
+        log_info("placed %d/%d\n", placed_cells, total_cells);
+    }
+    // Build up a fast position/type to Bel lookup table
+    int max_x = 0, max_y = 0;
+    for (auto bel : design->chip.getBels()) {
+        float x, y;
+        design->chip.estimatePosition(bel, x, y);
+        BelType type = design->chip.getBelType(bel);
+        if (state.fast_bels.size() < int(type) + 1)
+            state.fast_bels.resize(int(type) + 1);
+        if (state.fast_bels.at(int(type)).size() < int(x) + 1)
+            state.fast_bels.at(int(type)).resize(int(x) + 1);
+        if (state.fast_bels.at(int(type)).at(int(x)).size() < int(y) + 1)
+            state.fast_bels.at(int(type)).at(int(x)).resize(int(y) + 1);
+        max_x = std::max(max_x, int(x));
+        max_y = std::max(max_y, int(y));
+        state.fast_bels.at(int(type)).at(int(x)).at(int((y))).push_back(bel);
+    }
+    state.diameter = std::max(max_x, max_y) + 1;
+    // Calculate wirelength after initial placement
+    state.curr_wirelength = 0;
+    for (auto net : design->nets) {
+        float wl = get_wirelength(&design->chip, net.second);
+        state.wirelengths[net.second] = wl;
+        state.curr_wirelength += wl;
     }
 
-    for (auto bel_type_name : types_used) {
-        auto blist = design->chip.getBels();
-        BelType bel_type = belTypeFromId(bel_type_name);
-        auto bi = blist.begin();
+    int n_no_progress = 0;
+    double avg_wirelength = state.curr_wirelength;
+    state.temp = 10000;
 
-        for (auto cell_entry : design->cells) {
-            CellInfo *cell = cell_entry.second;
+    // Main simulated annealing loop
+    for (int iter = 1;; iter++) {
+        state.n_move = state.n_accept = 0;
+        state.improved = false;
 
-            // Ignore already placed cells
-            if (cell->bel != BelId())
-                continue;
-            // Only place one type of Bel at a time
-            if (cell->type != bel_type_name)
-                continue;
+        // if (iter % 50 == 0)
+        log("  at iteration #%d: temp = %f, wire length = %f\n", iter,
+            state.temp, state.curr_wirelength);
 
-            while ((bi != blist.end()) &&
-                   ((design->chip.getBelType(*bi) != bel_type ||
-                     !design->chip.checkBelAvail(*bi)) ||
-                    !isValidBelForCell(design, cell, *bi)))
-                bi++;
-            if (bi == blist.end())
-                log_error("Too many \'%s\' used in design\n",
-                          cell->type.c_str());
-            cell->bel = *bi++;
-            design->chip.bindBel(cell->bel, cell->name);
+        for (int m = 0; m < 15; ++m) {
+            // Loop through all automatically placed cells
+            for (auto cell : autoplaced) {
+                // Find another random Bel for this cell
+                BelId try_bel = random_bel_for_cell(design, cell, state, rnd);
+                // If valid, try and swap to a new position and see if
+                // the new position is valid/worthwhile
+                if (try_bel != BelId() && try_bel != cell->bel)
+                    try_swap_position(design, cell, try_bel, rnd, state);
+            }
+        }
+        // Heuristic to improve placement on the 8k
+        if (state.improved) {
+            n_no_progress = 0;
+            // std::cout << "improved\n";
+        } else
+            ++n_no_progress;
 
-            // Back annotate location
-            cell->attrs["BEL"] = design->chip.getBelName(cell->bel).str();
+        if (state.temp <= 1e-3 && n_no_progress >= 5)
+            break;
+
+        double Raccept = (double)state.n_accept / (double)state.n_move;
+
+        int M = std::max(max_x, max_y) + 1;
+
+        double upper = 0.6, lower = 0.4;
+
+        if (state.curr_wirelength < 0.95 * avg_wirelength)
+            avg_wirelength = 0.8 * avg_wirelength + 0.2 * state.curr_wirelength;
+        else {
+            if (Raccept >= 0.8) {
+                state.temp *= 0.7;
+            } else if (Raccept > upper) {
+                if (state.diameter < M)
+                    ++state.diameter;
+                else
+                    state.temp *= 0.9;
+            } else if (Raccept > lower) {
+                state.temp *= 0.95;
+            } else {
+                // Raccept < 0.3
+                if (state.diameter > 1)
+                    --state.diameter;
+                else
+                    state.temp *= 0.8;
+            }
         }
     }
 }

common/place.h

@@ -23,7 +23,7 @@
 
 NEXTPNR_NAMESPACE_BEGIN
 
-extern void place_design(Design *design);
+extern void place_design_sa(Design *design);
 
 NEXTPNR_NAMESPACE_END
 

common/route.cc

@@ -196,6 +196,7 @@ struct Router
                                 float(next_delay));
 #endif
                         revisitCnt++;
+                        continue;
                     }
 
                     if (!chip.checkWireAvail(next_wire)) {

ice40/arch_place.cc

@@ -18,11 +18,12 @@
  */
 
 #include "arch_place.h"
+#include "cells.h"
 
 NEXTPNR_NAMESPACE_BEGIN
 
-static const NetInfo *
-get_net_or_nullptr(const CellInfo *cell, const IdString port)
+static const NetInfo *get_net_or_nullptr(const CellInfo *cell,
+                                         const IdString port)
 {
     auto found = cell->ports.find(port);
     if (found != cell->ports.end())
@@ -45,9 +46,12 @@ static bool logicCellsCompatible(const std::vector<const CellInfo *> &cells)
                 clk = get_net_or_nullptr(cell, "CLK");
                 sr = get_net_or_nullptr(cell, "SR");
 
-                locals.insert(cen);
-                locals.insert(clk);
-                locals.insert(sr);
+                if (!is_global_net(cen))
+                    locals.insert(cen);
+                if (!is_global_net(clk))
+                    locals.insert(clk);
+                if (!is_global_net(sr))
+                    locals.insert(sr);
 
                 if (std::stoi(cell->params.at("NEG_CLK"))) {
                     dffs_neg = true;
@@ -93,7 +97,8 @@ bool isValidBelForCell(Design *design, CellInfo *cell, BelId bel)
 
         cells.push_back(cell);
         return logicCellsCompatible(cells);
-
+    } else if (cell->type == "SB_IO") {
+        return design->chip.getBelPackagePin(bel) != "";
     } else {
         // TODO: IO cell clock checks
         return true;

ice40/bitstream.cc

@@ -67,6 +67,28 @@ void set_config(const TileInfoPOD &ti,
     }
 }
 
+int get_param_or_def(const CellInfo *cell, const std::string &param,
+                     int defval = 0)
+{
+    auto found = cell->params.find(param);
+    if (found != cell->params.end())
+        return std::stoi(found->second);
+    else
+        return defval;
+}
+
+std::string get_param_str_or_def(const CellInfo *cell, const std::string &param,
+                                 std::string defval = "")
+{
+    auto found = cell->params.find(param);
+    if (found != cell->params.end())
+        return found->second;
+    else
+        return defval;
+}
+
+char get_hexdigit(int i) { return std::string("0123456789ABCDEF").at(i); }
+
 void write_asc(const Design &design, std::ostream &out)
 {
     const Chip &chip = design.chip;
@@ -134,12 +156,12 @@ void write_asc(const Design &design, std::ostream &out)
         int x = beli.x, y = beli.y, z = beli.z;
         if (cell.second->type == "ICESTORM_LC") {
             TileInfoPOD &ti = bi.tiles_nonrouting[TILE_LOGIC];
-            unsigned lut_init = std::stoi(cell.second->params["LUT_INIT"]);
-            bool neg_clk = std::stoi(cell.second->params["NEG_CLK"]);
-            bool dff_enable = std::stoi(cell.second->params["DFF_ENABLE"]);
-            bool async_sr = std::stoi(cell.second->params["ASYNC_SR"]);
-            bool set_noreset = std::stoi(cell.second->params["SET_NORESET"]);
-            bool carry_enable = std::stoi(cell.second->params["CARRY_ENABLE"]);
+            unsigned lut_init = get_param_or_def(cell.second, "LUT_INIT");
+            bool neg_clk = get_param_or_def(cell.second, "NEG_CLK");
+            bool dff_enable = get_param_or_def(cell.second, "DFF_ENABLE");
+            bool async_sr = get_param_or_def(cell.second, "ASYNC_SR");
+            bool set_noreset = get_param_or_def(cell.second, "SET_NORESET");
+            bool carry_enable = get_param_or_def(cell.second, "CARRY_ENABLE");
             std::vector<bool> lc(20, false);
             // From arachne-pnr
             static std::vector<int> lut_perm = {
@@ -160,9 +182,9 @@ void write_asc(const Design &design, std::ostream &out)
             set_config(ti, config.at(y).at(x), "NegClk", neg_clk);
         } else if (cell.second->type == "SB_IO") {
             TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO];
-            unsigned pin_type = std::stoi(cell.second->params["PIN_TYPE"]);
-            bool neg_trigger = std::stoi(cell.second->params["NEG_TRIGGER"]);
-            bool pullup = std::stoi(cell.second->params["PULLUP"]);
+            unsigned pin_type = get_param_or_def(cell.second, "PIN_TYPE");
+            bool neg_trigger = get_param_or_def(cell.second, "NEG_TRIGGER");
+            bool pullup = get_param_or_def(cell.second, "PULLUP");
             for (int i = 0; i < 6; i++) {
                 bool val = (pin_type >> i) & 0x01;
                 set_config(ti, config.at(y).at(x),
@@ -198,11 +220,37 @@ void write_asc(const Design &design, std::ostream &out)
             }
         } else if (cell.second->type == "SB_GB") {
             // no cell config bits
+        } else if (cell.second->type == "ICESTORM_RAM") {
+            const BelInfoPOD &beli = ci.bel_data[bel.index];
+            int x = beli.x, y = beli.y;
+            const TileInfoPOD &ti_ramt = bi.tiles_nonrouting[TILE_RAMT];
+            const TileInfoPOD &ti_ramb = bi.tiles_nonrouting[TILE_RAMB];
+            if (!(chip.args.type == ChipArgs::LP1K ||
+                  chip.args.type == ChipArgs::HX1K)) {
+                set_config(ti_ramb, config.at(y).at(x), "RamConfig.PowerUp",
+                           true);
+            }
+            bool negclk_r = get_param_or_def(cell.second, "NEG_CLK_R");
+            bool negclk_w = get_param_or_def(cell.second, "NEG_CLK_W");
+            int write_mode = get_param_or_def(cell.second, "WRITE_MODE");
+            int read_mode = get_param_or_def(cell.second, "READ_MODE");
+            set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_w);
+            set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_r);
+
+            set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_0",
+                       write_mode & 0x1);
+            set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_1",
+                       write_mode & 0x2);
+            set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_2",
+                       read_mode & 0x1);
+            set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_3",
+                       read_mode & 0x2);
+
         } else {
             assert(false);
         }
     }
-    // Set config bits in unused IO
+    // Set config bits in unused IO and RAM
     for (auto bel : chip.getBels()) {
         if (chip.bel_to_cell[bel.index] == IdString() &&
             chip.getBelType(bel) == TYPE_SB_IO) {
@@ -221,6 +269,15 @@ void write_asc(const Design &design, std::ostream &out)
                                "IoCtrl.REN_" + std::to_string(iez), false);
                 }
             }
+        } else if (chip.bel_to_cell[bel.index] == IdString() &&
+                   chip.getBelType(bel) == TYPE_ICESTORM_RAM) {
+            const BelInfoPOD &beli = ci.bel_data[bel.index];
+            int x = beli.x, y = beli.y;
+            TileInfoPOD &ti = bi.tiles_nonrouting[TILE_RAMB];
+            if ((chip.args.type == ChipArgs::LP1K ||
+                 chip.args.type == ChipArgs::HX1K)) {
+                set_config(ti, config.at(y).at(x), "RamConfig.PowerUp", true);
+            }
         }
     }
 
@@ -312,6 +369,35 @@ void write_asc(const Design &design, std::ostream &out)
             out << std::endl;
         }
     }
+
+    // Write RAM init data
+    for (auto cell : design.cells) {
+        if (cell.second->bel != BelId()) {
+            if (cell.second->type == "ICESTORM_RAM") {
+                const BelInfoPOD &beli = ci.bel_data[cell.second->bel.index];
+                int x = beli.x, y = beli.y;
+                out << ".ram_data " << x << " " << y << std::endl;
+                for (int w = 0; w < 16; w++) {
+                    std::vector<bool> bits(256);
+                    std::string init = get_param_str_or_def(
+                            cell.second,
+                            std::string("INIT_") + get_hexdigit(w));
+                    assert(init != "");
+                    for (int i = 0; i < init.size(); i++) {
+                        bool val = (init.at((init.size() - 1) - i) == '1');
+                        bits.at(i) = val;
+                    }
+                    for (int i = bits.size()-4; i >= 0; i -= 4) {
+                        int c = bits.at(i) + (bits.at(i + 1) << 1) +
+                                (bits.at(i + 2) << 2) + (bits.at(i + 3) << 3);
+                        out << char(std::tolower(get_hexdigit(c)));
+                    }
+                    out << std::endl;
+                }
+                out << std::endl;
+            }
+        }
+    }
 }
 
 NEXTPNR_NAMESPACE_END

ice40/cells.cc

@@ -190,7 +190,7 @@ void nxio_to_sb(CellInfo *nxio, CellInfo *sbio)
     }
 }
 
-bool is_global_net(NetInfo *net)
+bool is_global_net(const NetInfo *net)
 {
     return bool(net_driven_by(net, is_gbuf, "GLOBAL_BUFFER_OUTPUT"));
 }

ice40/cells.h

@@ -75,7 +75,7 @@ void dff_to_lc(CellInfo *dff, CellInfo *lc, bool pass_thru_lut = false);
 void nxio_to_sb(CellInfo *nxio, CellInfo *sbio);
 
 // Return true if a net is a global net
-bool is_global_net(NetInfo *net);
+bool is_global_net(const NetInfo *net);
 
 NEXTPNR_NAMESPACE_END
 

ice40/chip.cc

@@ -273,6 +273,15 @@ BelId Chip::getPackagePinBel(const std::string &pin) const
     return BelId();
 }
 
+std::string Chip::getBelPackagePin(BelId bel) const
+{
+    for (int i = 0; i < package_info->num_pins; i++) {
+        if (package_info->pins[i].bel_index == bel.index) {
+            return std::string(package_info->pins[i].name);
+        }
+    }
+    return "";
+}
 // -----------------------------------------------------------------------
 
 bool Chip::estimatePosition(BelId bel, int &x, int &y) const

ice40/chip.h

@@ -713,6 +713,7 @@ struct Chip
     }
 
     BelId getPackagePinBel(const std::string &pin) const;
+    std::string getBelPackagePin(BelId bel) const;
 
     // -------------------------------------------------
 

ice40/main.cc

@@ -222,7 +222,7 @@ int main(int argc, char *argv[])
 
         pack_design(&design);
         if (!vm.count("pack-only")) {
-            place_design(&design);
+            place_design_sa(&design);
             route_design(&design, verbose);
         }
     }

ice40/pack.cc

@@ -129,8 +129,8 @@ static void pack_ram(Design *design)
                                                ci->name.str() + "_RAM");
             packed_cells.insert(ci->name);
             new_cells.push_back(packed);
-            packed->params["READ_MODE"] = ci->params.at("READ_MODE");
-            packed->params["WRITE_MODE"] = ci->params.at("WRITE_MODE");
+            for (auto param : ci->params)
+                packed->params[param.first] = param.second;
             packed->params["NEG_CLK_W"] =
                     std::to_string(ci->type == "SB_RAM40_4KNW" ||
                                    ci->type == "SB_RAM40_4KNRNW");