caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Gowin. BUGFIX. Create all Clock Pips. (#1358)

Browse Source 
Some Clocks PIPS were not created due to a check for the presence of a
delay class, now all wires are attributed to the class so that there is
no longer any need for this check.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This commit is contained in:
YRabbit 2024-09-06 06:39:26 +10:00 committed by GitHub
parent 4cf7afedf7
commit 4d1de4532a
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
1 changed files with 1 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
himbaechel/uarch/gowin/gowin_arch_gen.py
View File

@ -365,8 +365,7 @@ def create_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
if not tt.has_wire(src):
tt.create_wire(src, "GLOBAL_CLK")
src_tm_class = get_tm_class(db, src)
if src_tm_class in {'CENT_SPINE_PCLK', 'SPINE_TAP_PCLK', 'TAP_BRANCH_PCLK', 'BRANCH_PCLK'}:
tt.create_pip(src, dst, src_tm_class)
tt.create_pip(src, dst, src_tm_class)
def create_hclk_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
if (y, x) not in db.hclk_pips: