Add yosys script

xc7/picorv32.ys

@@ -0,0 +1,54 @@
+read_verilog picorv32.v
+read_verilog picorv32_top.v
+
+#synth_xilinx -top picorv32
+
+#begin:
+    read_verilog -lib +/xilinx/cells_sim.v
+    read_verilog -lib +/xilinx/cells_xtra.v
+#    read_verilog -lib +/xilinx/brams_bb.v
+#    read_verilog -lib +/xilinx/drams_bb.v
+    hierarchy -check -top top
+
+#flatten:     (only if -flatten)
+    proc
+    flatten
+
+#coarse:
+    synth -run coarse
+
+#bram:
+#    memory_bram -rules +/xilinx/brams.txt
+#    techmap -map +/xilinx/brams_map.v
+#
+#dram:
+#    memory_bram -rules +/xilinx/drams.txt
+#    techmap -map +/xilinx/drams_map.v
+
+fine:
+    opt -fast -full
+    memory_map
+    dffsr2dff
+#    dff2dffe
+    opt -full
+    techmap -map +/techmap.v #-map +/xilinx/arith_map.v
+    opt -fast
+
+map_luts:
+    abc -luts 2:2,3,6:5 #,10,20 [-dff]
+    clean
+
+map_cells:
+    techmap -map +/xilinx/cells_map.v
+    dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT
+    clean
+
+check:
+    hierarchy -check
+    stat
+    check -noinit
+
+#edif:     (only if -edif)
+#    write_edif <file-name>
+
+write_json picorv32.json