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WIP: adding timing budget to placer

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Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-06-20 17:08:57 +02:00
parent 15c5c9c425
commit 4fc9625040
4 changed files with 23 additions and 7 deletions
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9
common/place_sa.cc
View File

@ -314,7 +314,9 @@ class SAPlacer
load_cell->bel, ctx->portPinFromId(load.port)); load_cell->bel, ctx->portPinFromId(load.port));
// wirelength += std::abs(load_x - driver_x) + std::abs(load_y - // wirelength += std::abs(load_x - driver_x) + std::abs(load_y -
// driver_y); // driver_y);
wirelength += ctx->estimateDelay(drv_wire, user_wire); delay_t raw_wl = ctx->estimateDelay(drv_wire, user_wire);
wirelength += 100 * (ctx->getDelayNS(raw_wl) / ctx->getDelayNS(load.budget));
// wirelength += pow(ctx->estimateDelay(drv_wire, user_wire), 2.0);
} }
return wirelength; return wirelength;
} }
@ -376,9 +378,8 @@ class SAPlacer
delta = new_wirelength - curr_wirelength; delta = new_wirelength - curr_wirelength;
n_move++; n_move++;
// SA acceptance criterea // SA acceptance criterea
if (delta < 0 || if (delta < 0 || (temp > 1e-6 && (ctx->rng() / float(0x3fffffff)) <=
(temp > 1e-6 && std::exp(-delta / temp))) {
(ctx->rng() / float(0x3fffffff)) <= std::exp(-delta / temp))) {
n_accept++; n_accept++;
if (delta < 0) if (delta < 0)
improved = true; improved = true;

7
common/timing.cc
View File

@ -101,6 +101,8 @@ void assign_budget(Context *ctx, float default_clock)
} }
} }
} }
const bool debug = true;
// Post-allocation check // Post-allocation check
for (auto net : ctx->nets) { for (auto net : ctx->nets) {
for (auto user : net.second->users) { for (auto user : net.second->users) {
@ -109,6 +111,11 @@ void assign_budget(Context *ctx, float default_clock)
"timing budget of %fns\n", "timing budget of %fns\n",
user.cell->name.c_str(ctx), user.port.c_str(ctx), user.cell->name.c_str(ctx), user.port.c_str(ctx),
net.first.c_str(ctx), ctx->getDelayNS(user.budget)); net.first.c_str(ctx), ctx->getDelayNS(user.budget));
if (debug)
log_warning("port %s.%s, connected to net '%s', has "
"timing budget of %fns\n",
user.cell->name.c_str(ctx), user.port.c_str(ctx),
net.first.c_str(ctx), ctx->getDelayNS(user.budget));
} }
} }
} }

2
ice40/arch.cc
View File

@ -313,7 +313,7 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
delay_t x2 = chip_info->wire_data[dst.index].x; delay_t x2 = chip_info->wire_data[dst.index].x;
delay_t y2 = chip_info->wire_data[dst.index].y; delay_t y2 = chip_info->wire_data[dst.index].y;
return fabsf(x1 - x2) + fabsf(y1 - y2); return delay_t(50 * (fabsf(x1 - x2) + fabsf(y1 - y2)));
} }
// ----------------------------------------------------------------------- // -----------------------------------------------------------------------

12
ice40/main.cc
View File

@ -224,8 +224,16 @@ int main(int argc, char *argv[])
if (vm.count("tmfuzz")) { if (vm.count("tmfuzz")) {
std::vector<WireId> src_wires, dst_wires; std::vector<WireId> src_wires, dst_wires;
for (auto w : ctx.getWires()) /*for (auto w : ctx.getWires())
src_wires.push_back(w); src_wires.push_back(w);*/
for (auto b : ctx.getBels()) {
if (ctx.getBelType(b) == TYPE_ICESTORM_LC) {
src_wires.push_back(ctx.getWireBelPin(b, PIN_O));
}
if (ctx.getBelType(b) == TYPE_SB_IO) {
src_wires.push_back(ctx.getWireBelPin(b, PIN_D_IN_0));
}
}
for (auto b : ctx.getBels()) { for (auto b : ctx.getBels()) {
if (ctx.getBelType(b) == TYPE_ICESTORM_LC) { if (ctx.getBelType(b) == TYPE_ICESTORM_LC) {