export all the rest for bitstream
This commit is contained in:
Miodrag Milanovic
parent
987d7099e2
commit
50485371fa
@ -334,6 +334,12 @@ struct BitstreamJsonBackend
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}
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}
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void write_xlut(CellInfo *cell) {
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open_instance(cell);
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add_config("lut_table", extract_bits_or_default(cell->params, id_lut_table, 16));
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close_instance();
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}
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void write_iom(CellInfo *cell) {
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open_instance(cell);
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add_config("pads_path", str_or_default(cell->params, ctx->id("pads_path"), ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;"));
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@ -429,113 +435,51 @@ struct BitstreamJsonBackend
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add_config("raw_config3", extract_bits_or_default(cell->params, ctx->id("raw_config3"), 3));
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close_instance();
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}
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/*
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// mode 0
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"config": {
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"ck0_edge": false,
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"ck1_edge": false,
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"ack_sel": false,
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"bck_sel": false,
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"use_adest_arst": false,
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"use_bdest_arst": false
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},
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"location": "TILE[47x26]:S4.CDC1",
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"type": "DDE"
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},
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// mode 1
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"i_b2g_cdc": {
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"config": {
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"ck0_edge": false,
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"ck1_edge": false,
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"ack_sel": false,
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"bck_sel": false,
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"use_asrc_arst": false,
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"use_bsrc_arst": false,
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"use_adest_arst": false,
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"use_bdest_arst": false
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},
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"location": "TILE[47x26]:S4.CDC1",
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"type": "TDE"
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},
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// mode 2
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"i_b2g_cdc": {
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"config": {
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"ck0_edge": false,
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"ck1_edge": false,
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"ack_sel": false,
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"bck_sel": false,
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"use_asrc_arst": false,
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"use_bsrc_arst": false,
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"use_adest_arst": false,
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"use_bdest_arst": false
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},
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"location": "TILE[47x26]:S4.CDC1",
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"type": "CDC"
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},
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// mode 3
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"i_b2g_cdc": {
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"location": "TILE[47x26]:S4.CDC1",
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"type": "BGC"
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},
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// mode 4
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"i_b2g_cdc": {
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"location": "TILE[47x26]:S4.CDC1",
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"type": "GBC"
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},
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// mode 5
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"i_b2g_cdc": {
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"config": {
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"ck0_edge": false,
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"ck1_edge": false,
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"ack_sel": false,
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"bck_sel": false,
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"cck_sel": false,
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"dck_sel": false,
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"use_asrc_arst": false,
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"use_bsrc_arst": false,
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"use_csrc_arst": false,
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"use_dsrc_arst": false,
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"use_adest_arst": false,
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"use_bdest_arst": false,
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"use_cdest_arst": false,
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"use_ddest_arst": false,
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"link_BA": false,
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"link_CB": false,
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"link_DC": false
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},
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"location": "TILE[47x26]:S8.XCDC1",
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"type": "XCDC"
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},
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void write_cdc(CellInfo *cell) {
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open_instance(cell);
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if (cell->type.in(id_DDE, id_TDE, id_CDC, id_XCDC)) {
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add_config("ck0_edge", bool_or_default(cell->params, ctx->id("ck0_edge"), false));
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add_config("ck1_edge", bool_or_default(cell->params, ctx->id("ck1_edge"), false));
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add_config("ack_sel", bool_or_default(cell->params, ctx->id("ack_sel"), false));
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add_config("bck_sel", bool_or_default(cell->params, ctx->id("bck_sel"), false));
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if (cell->type.in(id_XCDC)) {
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add_config("cck_sel", bool_or_default(cell->params, ctx->id("cck_sel"), false));
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add_config("dck_sel", bool_or_default(cell->params, ctx->id("dck_sel"), false));
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}
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if (cell->type.in(id_TDE, id_CDC, id_XCDC)) {
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add_config("use_asrc_arst", bool_or_default(cell->params, ctx->id("use_asrc_arst"), false));
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add_config("use_bsrc_arst", bool_or_default(cell->params, ctx->id("use_bsrc_arst"), false));
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}
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if (cell->type.in(id_XCDC)) {
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add_config("use_csrc_arst", bool_or_default(cell->params, ctx->id("use_csrc_arst"), false));
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add_config("use_dsrc_arst", bool_or_default(cell->params, ctx->id("use_dsrc_arst"), false));
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}
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add_config("use_adest_arst", bool_or_default(cell->params, ctx->id("use_adest_arst"), false));
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add_config("use_bdest_arst", bool_or_default(cell->params, ctx->id("use_bdest_arst"), false));
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if (cell->type.in(id_XCDC)) {
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add_config("use_cdest_arst", bool_or_default(cell->params, ctx->id("use_cdest_arst"), false));
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add_config("use_ddest_arst", bool_or_default(cell->params, ctx->id("use_ddest_arst"), false));
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}
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add_config("link_BA", bool_or_default(cell->params, ctx->id("link_BA"), false));
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add_config("link_CB", bool_or_default(cell->params, ctx->id("link_CB"), false));
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add_config("link_DC", bool_or_default(cell->params, ctx->id("link_DC"), false));
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}
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close_instance();
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}
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// FIFO mode 0
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ERROR generating that one
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// FIFO mode 1
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"i_fifo_fifo": {
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"config": {
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"rck_edge": false,
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"wck_edge": false,
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"use_read_arst": false,
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"use_write_arst": false,
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"read_addr_inv": 0
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},
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"location": "TILE[46x26]:S8.XFIFO1",
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"type": "XHFIFO"
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},
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// FIFO mode 2
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"i_fifo_fifo": {
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"config": {
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"rck_edge": false,
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"wck_edge": false,
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"use_read_arst": false,
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"use_write_arst": false,
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"read_addr_inv": 0
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},
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"location": "TILE[46x26]:S8.XFIFO1",
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"type": "XWFIFO"
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},
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*/
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void write_fifo(CellInfo *cell) {
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open_instance(cell);
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add_config("rck_edge", bool_or_default(cell->params, ctx->id("rck_edge"), false));
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add_config("wck_edge", bool_or_default(cell->params, ctx->id("wck_edge"), false));
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if (cell->type.in(id_XHFIFO, id_XWFIFO)) {
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add_config("use_read_arst", bool_or_default(cell->params, ctx->id("use_read_arst"), false));
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add_config("use_write_arst", bool_or_default(cell->params, ctx->id("use_write_arst"), false));
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}
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add_config("read_addr_inv", int_or_default(cell->params, ctx->id("read_addr_inv"), 0));
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//add_config("read_addr_inv", extract_bits_or_default(cell->params, ctx->id("read_addr_inv"), cell->type == id_FIFO ? 6 : 7));
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close_instance();
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}
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void write_interconnections()
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{
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@ -597,15 +541,20 @@ struct BitstreamJsonBackend
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case id_XHRF.index:
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case id_XWRF.index:
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case id_XPRF.index: write_rfb(cell.second.get()); break;
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//case id_XLUT.index:
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//case id_FIFO.index:
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//case id_XFIFO.index:
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//case id_CDC.index:
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//case id_XCDC.index:
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//case id_CRX.index:
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//case id_CTX.index:
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case id_XLUT.index: write_xlut(cell.second.get()); break;
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case id_FIFO.index: // mode 0
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case id_XHFIFO.index: // mode 1
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case id_XWFIFO.index: write_fifo(cell.second.get()); break; // mode 2
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case id_DDE.index: // mode 0
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case id_TDE.index: // mode 1
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case id_CDC.index: // mode 2
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case id_BGC.index: // mode 3
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case id_GBC.index: // mode 4
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case id_XCDC.index: write_cdc(cell.second.get()); break; // mode 5
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case id_DSP.index: write_dsp(cell.second.get()); break;
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case id_PLL.index: write_pll(cell.second.get()); break;
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//case id_CRX.index:
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//case id_CTX.index:
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//case id_PMA.index:
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//case id_Service.index:
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//case id_SOCIF.index:
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