Create machxo2 backend (renamed from generic).
Signed-off-by: William D. Jones <thor0505@comcast.net>
This commit is contained in:
gatecat
parent
c956cae824
commit
510969ab97
@ -66,9 +66,9 @@ endif()
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set(PROGRAM_PREFIX "" CACHE STRING "Name prefix for executables")
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# List of families to build
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set(FAMILIES generic ice40 ecp5 nexus gowin fpga_interchange)
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set(FAMILIES generic ice40 ecp5 nexus gowin fpga_interchange machxo2)
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set(STABLE_FAMILIES generic ice40 ecp5)
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set(EXPERIMENTAL_FAMILIES nexus gowin fpga_interchange)
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set(EXPERIMENTAL_FAMILIES nexus gowin fpga_interchange machxo2)
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set(ARCH "" CACHE STRING "Architecture family for nextpnr build")
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set_property(CACHE ARCH PROPERTY STRINGS ${FAMILIES})
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@ -59,7 +59,8 @@ template <> struct hash<std::pair<int, NEXTPNR_NAMESPACE_PREFIX BelId>>
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return seed;
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}
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};
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#if !defined(ARCH_GOWIN)
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#if !(defined(ARCH_GENERIC) || defined(ARCH_MACHXO2) || defined(ARCH_GOWIN))
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template <> struct hash<std::pair<NEXTPNR_NAMESPACE_PREFIX IdString, NEXTPNR_NAMESPACE_PREFIX BelId>>
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{
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std::size_t
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730
machxo2/arch.cc
Normal file
730
machxo2/arch.cc
Normal file
@ -0,0 +1,730 @@
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/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include <iostream>
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#include <math.h>
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#include "nextpnr.h"
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#include "placer1.h"
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#include "placer_heap.h"
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#include "router1.h"
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#include "router2.h"
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#include "util.h"
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NEXTPNR_NAMESPACE_BEGIN
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WireInfo &Arch::wire_info(IdString wire)
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{
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auto w = wires.find(wire);
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if (w == wires.end())
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NPNR_ASSERT_FALSE_STR("no wire named " + wire.str(this));
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return w->second;
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}
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PipInfo &Arch::pip_info(IdString pip)
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{
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auto p = pips.find(pip);
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if (p == pips.end())
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NPNR_ASSERT_FALSE_STR("no pip named " + pip.str(this));
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return p->second;
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}
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BelInfo &Arch::bel_info(IdString bel)
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{
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auto b = bels.find(bel);
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if (b == bels.end())
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NPNR_ASSERT_FALSE_STR("no bel named " + bel.str(this));
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return b->second;
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}
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void Arch::addWire(IdString name, IdString type, int x, int y)
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{
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NPNR_ASSERT(wires.count(name) == 0);
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WireInfo &wi = wires[name];
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wi.name = name;
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wi.type = type;
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wi.x = x;
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wi.y = y;
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wire_ids.push_back(name);
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}
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void Arch::addPip(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay, Loc loc)
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{
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NPNR_ASSERT(pips.count(name) == 0);
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PipInfo &pi = pips[name];
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pi.name = name;
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pi.type = type;
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pi.srcWire = srcWire;
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pi.dstWire = dstWire;
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pi.delay = delay;
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pi.loc = loc;
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wire_info(srcWire).downhill.push_back(name);
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wire_info(dstWire).uphill.push_back(name);
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pip_ids.push_back(name);
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if (int(tilePipDimZ.size()) <= loc.x)
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tilePipDimZ.resize(loc.x + 1);
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if (int(tilePipDimZ[loc.x].size()) <= loc.y)
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tilePipDimZ[loc.x].resize(loc.y + 1);
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gridDimX = std::max(gridDimX, loc.x + 1);
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gridDimY = std::max(gridDimY, loc.x + 1);
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tilePipDimZ[loc.x][loc.y] = std::max(tilePipDimZ[loc.x][loc.y], loc.z + 1);
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}
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void Arch::addAlias(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay)
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{
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NPNR_ASSERT(pips.count(name) == 0);
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PipInfo &pi = pips[name];
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pi.name = name;
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pi.type = type;
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pi.srcWire = srcWire;
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pi.dstWire = dstWire;
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pi.delay = delay;
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wire_info(srcWire).aliases.push_back(name);
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pip_ids.push_back(name);
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}
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void Arch::addBel(IdString name, IdString type, Loc loc, bool gb)
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{
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NPNR_ASSERT(bels.count(name) == 0);
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NPNR_ASSERT(bel_by_loc.count(loc) == 0);
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BelInfo &bi = bels[name];
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bi.name = name;
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bi.type = type;
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bi.x = loc.x;
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bi.y = loc.y;
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bi.z = loc.z;
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bi.gb = gb;
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bel_ids.push_back(name);
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bel_by_loc[loc] = name;
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if (int(bels_by_tile.size()) <= loc.x)
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bels_by_tile.resize(loc.x + 1);
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if (int(bels_by_tile[loc.x].size()) <= loc.y)
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bels_by_tile[loc.x].resize(loc.y + 1);
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bels_by_tile[loc.x][loc.y].push_back(name);
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if (int(tileBelDimZ.size()) <= loc.x)
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tileBelDimZ.resize(loc.x + 1);
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if (int(tileBelDimZ[loc.x].size()) <= loc.y)
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tileBelDimZ[loc.x].resize(loc.y + 1);
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gridDimX = std::max(gridDimX, loc.x + 1);
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gridDimY = std::max(gridDimY, loc.x + 1);
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tileBelDimZ[loc.x][loc.y] = std::max(tileBelDimZ[loc.x][loc.y], loc.z + 1);
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}
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void Arch::addBelInput(IdString bel, IdString name, IdString wire)
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{
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NPNR_ASSERT(bel_info(bel).pins.count(name) == 0);
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PinInfo &pi = bel_info(bel).pins[name];
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pi.name = name;
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pi.wire = wire;
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pi.type = PORT_IN;
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wire_info(wire).downhill_bel_pins.push_back(BelPin{bel, name});
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wire_info(wire).bel_pins.push_back(BelPin{bel, name});
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}
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void Arch::addBelOutput(IdString bel, IdString name, IdString wire)
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{
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NPNR_ASSERT(bel_info(bel).pins.count(name) == 0);
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PinInfo &pi = bel_info(bel).pins[name];
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pi.name = name;
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pi.wire = wire;
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pi.type = PORT_OUT;
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wire_info(wire).uphill_bel_pin = BelPin{bel, name};
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wire_info(wire).bel_pins.push_back(BelPin{bel, name});
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}
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void Arch::addBelInout(IdString bel, IdString name, IdString wire)
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{
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NPNR_ASSERT(bel_info(bel).pins.count(name) == 0);
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PinInfo &pi = bel_info(bel).pins[name];
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pi.name = name;
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pi.wire = wire;
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pi.type = PORT_INOUT;
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wire_info(wire).downhill_bel_pins.push_back(BelPin{bel, name});
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wire_info(wire).bel_pins.push_back(BelPin{bel, name});
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}
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void Arch::addGroupBel(IdString group, IdString bel) { groups[group].bels.push_back(bel); }
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void Arch::addGroupWire(IdString group, IdString wire) { groups[group].wires.push_back(wire); }
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void Arch::addGroupPip(IdString group, IdString pip) { groups[group].pips.push_back(pip); }
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void Arch::addGroupGroup(IdString group, IdString grp) { groups[group].groups.push_back(grp); }
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void Arch::addDecalGraphic(DecalId decal, const GraphicElement &graphic)
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{
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decal_graphics[decal].push_back(graphic);
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refreshUi();
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}
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void Arch::setWireDecal(WireId wire, DecalXY decalxy)
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{
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wire_info(wire).decalxy = decalxy;
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refreshUiWire(wire);
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}
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void Arch::setPipDecal(PipId pip, DecalXY decalxy)
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{
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pip_info(pip).decalxy = decalxy;
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refreshUiPip(pip);
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}
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void Arch::setBelDecal(BelId bel, DecalXY decalxy)
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{
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bel_info(bel).decalxy = decalxy;
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refreshUiBel(bel);
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}
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void Arch::setGroupDecal(GroupId group, DecalXY decalxy)
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{
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groups[group].decalxy = decalxy;
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refreshUiGroup(group);
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}
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void Arch::setWireAttr(IdString wire, IdString key, const std::string &value) { wire_info(wire).attrs[key] = value; }
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void Arch::setPipAttr(IdString pip, IdString key, const std::string &value) { pip_info(pip).attrs[key] = value; }
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void Arch::setBelAttr(IdString bel, IdString key, const std::string &value) { bel_info(bel).attrs[key] = value; }
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void Arch::setLutK(int K) { args.K = K; }
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void Arch::setDelayScaling(double scale, double offset)
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{
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args.delayScale = scale;
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args.delayOffset = offset;
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}
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void Arch::addCellTimingClock(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_CLOCK_INPUT; }
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void Arch::addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayInfo delay)
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{
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if (get_or_default(cellTiming[cell].portClasses, fromPort, TMG_IGNORE) == TMG_IGNORE)
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cellTiming[cell].portClasses[fromPort] = TMG_COMB_INPUT;
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if (get_or_default(cellTiming[cell].portClasses, toPort, TMG_IGNORE) == TMG_IGNORE)
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cellTiming[cell].portClasses[toPort] = TMG_COMB_OUTPUT;
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cellTiming[cell].combDelays[CellDelayKey{fromPort, toPort}] = delay;
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}
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void Arch::addCellTimingSetupHold(IdString cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold)
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{
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TimingClockingInfo ci;
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ci.clock_port = clock;
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ci.edge = RISING_EDGE;
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ci.setup = setup;
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ci.hold = hold;
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cellTiming[cell].clockingInfo[port].push_back(ci);
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cellTiming[cell].portClasses[port] = TMG_REGISTER_INPUT;
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}
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void Arch::addCellTimingClockToOut(IdString cell, IdString port, IdString clock, DelayInfo clktoq)
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{
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TimingClockingInfo ci;
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ci.clock_port = clock;
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ci.edge = RISING_EDGE;
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ci.clockToQ = clktoq;
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cellTiming[cell].clockingInfo[port].push_back(ci);
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cellTiming[cell].portClasses[port] = TMG_REGISTER_OUTPUT;
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}
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// ---------------------------------------------------------------
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Arch::Arch(ArchArgs args) : chipName("generic"), args(args)
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{
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// Dummy for empty decals
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decal_graphics[IdString()];
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}
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void IdString::initialize_arch(const BaseCtx *ctx) {}
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// ---------------------------------------------------------------
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BelId Arch::getBelByName(IdString name) const
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{
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if (bels.count(name))
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return name;
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return BelId();
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}
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IdString Arch::getBelName(BelId bel) const { return bel; }
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Loc Arch::getBelLocation(BelId bel) const
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{
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auto &info = bels.at(bel);
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return Loc(info.x, info.y, info.z);
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}
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BelId Arch::getBelByLocation(Loc loc) const
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{
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auto it = bel_by_loc.find(loc);
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if (it != bel_by_loc.end())
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return it->second;
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return BelId();
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}
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const std::vector<BelId> &Arch::getBelsByTile(int x, int y) const { return bels_by_tile.at(x).at(y); }
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bool Arch::getBelGlobalBuf(BelId bel) const { return bels.at(bel).gb; }
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uint32_t Arch::getBelChecksum(BelId bel) const
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{
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// FIXME
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return 0;
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}
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void Arch::bindBel(BelId bel, CellInfo *cell, PlaceStrength strength)
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{
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bels.at(bel).bound_cell = cell;
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cell->bel = bel;
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cell->belStrength = strength;
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refreshUiBel(bel);
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}
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void Arch::unbindBel(BelId bel)
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{
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bels.at(bel).bound_cell->bel = BelId();
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bels.at(bel).bound_cell->belStrength = STRENGTH_NONE;
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bels.at(bel).bound_cell = nullptr;
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refreshUiBel(bel);
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}
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bool Arch::checkBelAvail(BelId bel) const { return bels.at(bel).bound_cell == nullptr; }
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CellInfo *Arch::getBoundBelCell(BelId bel) const { return bels.at(bel).bound_cell; }
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CellInfo *Arch::getConflictingBelCell(BelId bel) const { return bels.at(bel).bound_cell; }
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const std::vector<BelId> &Arch::getBels() const { return bel_ids; }
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IdString Arch::getBelType(BelId bel) const { return bels.at(bel).type; }
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const std::map<IdString, std::string> &Arch::getBelAttrs(BelId bel) const { return bels.at(bel).attrs; }
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WireId Arch::getBelPinWire(BelId bel, IdString pin) const
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{
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const auto &bdata = bels.at(bel);
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if (!bdata.pins.count(pin))
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log_error("bel '%s' has no pin '%s'\n", bel.c_str(this), pin.c_str(this));
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return bdata.pins.at(pin).wire;
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}
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PortType Arch::getBelPinType(BelId bel, IdString pin) const { return bels.at(bel).pins.at(pin).type; }
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std::vector<IdString> Arch::getBelPins(BelId bel) const
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{
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std::vector<IdString> ret;
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for (auto &it : bels.at(bel).pins)
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ret.push_back(it.first);
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return ret;
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}
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// ---------------------------------------------------------------
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WireId Arch::getWireByName(IdString name) const
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{
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if (wires.count(name))
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return name;
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return WireId();
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}
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IdString Arch::getWireName(WireId wire) const { return wire; }
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IdString Arch::getWireType(WireId wire) const { return wires.at(wire).type; }
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const std::map<IdString, std::string> &Arch::getWireAttrs(WireId wire) const { return wires.at(wire).attrs; }
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uint32_t Arch::getWireChecksum(WireId wire) const
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{
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// FIXME
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return 0;
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}
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void Arch::bindWire(WireId wire, NetInfo *net, PlaceStrength strength)
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{
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wires.at(wire).bound_net = net;
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net->wires[wire].pip = PipId();
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net->wires[wire].strength = strength;
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refreshUiWire(wire);
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}
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void Arch::unbindWire(WireId wire)
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{
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auto &net_wires = wires.at(wire).bound_net->wires;
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auto pip = net_wires.at(wire).pip;
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if (pip != PipId()) {
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pips.at(pip).bound_net = nullptr;
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refreshUiPip(pip);
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}
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net_wires.erase(wire);
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wires.at(wire).bound_net = nullptr;
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refreshUiWire(wire);
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}
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bool Arch::checkWireAvail(WireId wire) const { return wires.at(wire).bound_net == nullptr; }
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NetInfo *Arch::getBoundWireNet(WireId wire) const { return wires.at(wire).bound_net; }
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NetInfo *Arch::getConflictingWireNet(WireId wire) const { return wires.at(wire).bound_net; }
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const std::vector<BelPin> &Arch::getWireBelPins(WireId wire) const { return wires.at(wire).bel_pins; }
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const std::vector<WireId> &Arch::getWires() const { return wire_ids; }
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// ---------------------------------------------------------------
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PipId Arch::getPipByName(IdString name) const
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{
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if (pips.count(name))
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return name;
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return PipId();
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}
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IdString Arch::getPipName(PipId pip) const { return pip; }
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IdString Arch::getPipType(PipId pip) const { return pips.at(pip).type; }
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const std::map<IdString, std::string> &Arch::getPipAttrs(PipId pip) const { return pips.at(pip).attrs; }
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uint32_t Arch::getPipChecksum(PipId wire) const
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{
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// FIXME
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return 0;
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||||
}
|
||||
|
||||
void Arch::bindPip(PipId pip, NetInfo *net, PlaceStrength strength)
|
||||
{
|
||||
WireId wire = pips.at(pip).dstWire;
|
||||
pips.at(pip).bound_net = net;
|
||||
wires.at(wire).bound_net = net;
|
||||
net->wires[wire].pip = pip;
|
||||
net->wires[wire].strength = strength;
|
||||
refreshUiPip(pip);
|
||||
refreshUiWire(wire);
|
||||
}
|
||||
|
||||
void Arch::unbindPip(PipId pip)
|
||||
{
|
||||
WireId wire = pips.at(pip).dstWire;
|
||||
wires.at(wire).bound_net->wires.erase(wire);
|
||||
pips.at(pip).bound_net = nullptr;
|
||||
wires.at(wire).bound_net = nullptr;
|
||||
refreshUiPip(pip);
|
||||
refreshUiWire(wire);
|
||||
}
|
||||
|
||||
bool Arch::checkPipAvail(PipId pip) const { return pips.at(pip).bound_net == nullptr; }
|
||||
|
||||
NetInfo *Arch::getBoundPipNet(PipId pip) const { return pips.at(pip).bound_net; }
|
||||
|
||||
NetInfo *Arch::getConflictingPipNet(PipId pip) const { return pips.at(pip).bound_net; }
|
||||
|
||||
WireId Arch::getConflictingPipWire(PipId pip) const { return pips.at(pip).bound_net ? pips.at(pip).dstWire : WireId(); }
|
||||
|
||||
const std::vector<PipId> &Arch::getPips() const { return pip_ids; }
|
||||
|
||||
Loc Arch::getPipLocation(PipId pip) const { return pips.at(pip).loc; }
|
||||
|
||||
WireId Arch::getPipSrcWire(PipId pip) const { return pips.at(pip).srcWire; }
|
||||
|
||||
WireId Arch::getPipDstWire(PipId pip) const { return pips.at(pip).dstWire; }
|
||||
|
||||
DelayInfo Arch::getPipDelay(PipId pip) const { return pips.at(pip).delay; }
|
||||
|
||||
const std::vector<PipId> &Arch::getPipsDownhill(WireId wire) const { return wires.at(wire).downhill; }
|
||||
|
||||
const std::vector<PipId> &Arch::getPipsUphill(WireId wire) const { return wires.at(wire).uphill; }
|
||||
|
||||
const std::vector<PipId> &Arch::getWireAliases(WireId wire) const { return wires.at(wire).aliases; }
|
||||
|
||||
// ---------------------------------------------------------------
|
||||
|
||||
GroupId Arch::getGroupByName(IdString name) const { return name; }
|
||||
|
||||
IdString Arch::getGroupName(GroupId group) const { return group; }
|
||||
|
||||
std::vector<GroupId> Arch::getGroups() const
|
||||
{
|
||||
std::vector<GroupId> ret;
|
||||
for (auto &it : groups)
|
||||
ret.push_back(it.first);
|
||||
return ret;
|
||||
}
|
||||
|
||||
const std::vector<BelId> &Arch::getGroupBels(GroupId group) const { return groups.at(group).bels; }
|
||||
|
||||
const std::vector<WireId> &Arch::getGroupWires(GroupId group) const { return groups.at(group).wires; }
|
||||
|
||||
const std::vector<PipId> &Arch::getGroupPips(GroupId group) const { return groups.at(group).pips; }
|
||||
|
||||
const std::vector<GroupId> &Arch::getGroupGroups(GroupId group) const { return groups.at(group).groups; }
|
||||
|
||||
// ---------------------------------------------------------------
|
||||
|
||||
delay_t Arch::estimateDelay(WireId src, WireId dst) const
|
||||
{
|
||||
const WireInfo &s = wires.at(src);
|
||||
const WireInfo &d = wires.at(dst);
|
||||
int dx = abs(s.x - d.x);
|
||||
int dy = abs(s.y - d.y);
|
||||
return (dx + dy) * args.delayScale + args.delayOffset;
|
||||
}
|
||||
|
||||
delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
|
||||
{
|
||||
const auto &driver = net_info->driver;
|
||||
auto driver_loc = getBelLocation(driver.cell->bel);
|
||||
auto sink_loc = getBelLocation(sink.cell->bel);
|
||||
|
||||
int dx = abs(sink_loc.x - driver_loc.x);
|
||||
int dy = abs(sink_loc.y - driver_loc.y);
|
||||
return (dx + dy) * args.delayScale + args.delayOffset;
|
||||
}
|
||||
|
||||
bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; }
|
||||
|
||||
ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
|
||||
{
|
||||
ArcBounds bb;
|
||||
|
||||
int src_x = wires.at(src).x;
|
||||
int src_y = wires.at(src).y;
|
||||
int dst_x = wires.at(dst).x;
|
||||
int dst_y = wires.at(dst).y;
|
||||
|
||||
bb.x0 = src_x;
|
||||
bb.y0 = src_y;
|
||||
bb.x1 = src_x;
|
||||
bb.y1 = src_y;
|
||||
|
||||
auto extend = [&](int x, int y) {
|
||||
bb.x0 = std::min(bb.x0, x);
|
||||
bb.x1 = std::max(bb.x1, x);
|
||||
bb.y0 = std::min(bb.y0, y);
|
||||
bb.y1 = std::max(bb.y1, y);
|
||||
};
|
||||
extend(dst_x, dst_y);
|
||||
return bb;
|
||||
}
|
||||
|
||||
// ---------------------------------------------------------------
|
||||
|
||||
bool Arch::place()
|
||||
{
|
||||
std::string placer = str_or_default(settings, id("placer"), defaultPlacer);
|
||||
if (placer == "heap") {
|
||||
bool have_iobuf_or_constr = false;
|
||||
for (auto cell : sorted(cells)) {
|
||||
CellInfo *ci = cell.second;
|
||||
if (ci->type == id("GENERIC_IOB") || ci->bel != BelId() || ci->attrs.count(id("BEL"))) {
|
||||
have_iobuf_or_constr = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
bool retVal;
|
||||
if (!have_iobuf_or_constr) {
|
||||
log_warning("Unable to use HeAP due to a lack of IO buffers or constrained cells as anchors; reverting to "
|
||||
"SA.\n");
|
||||
retVal = placer1(getCtx(), Placer1Cfg(getCtx()));
|
||||
} else {
|
||||
PlacerHeapCfg cfg(getCtx());
|
||||
cfg.ioBufTypes.insert(id("GENERIC_IOB"));
|
||||
retVal = placer_heap(getCtx(), cfg);
|
||||
}
|
||||
getCtx()->settings[getCtx()->id("place")] = 1;
|
||||
archInfoToAttributes();
|
||||
return retVal;
|
||||
} else if (placer == "sa") {
|
||||
bool retVal = placer1(getCtx(), Placer1Cfg(getCtx()));
|
||||
getCtx()->settings[getCtx()->id("place")] = 1;
|
||||
archInfoToAttributes();
|
||||
return retVal;
|
||||
} else {
|
||||
log_error("Generic architecture does not support placer '%s'\n", placer.c_str());
|
||||
}
|
||||
}
|
||||
|
||||
bool Arch::route()
|
||||
{
|
||||
std::string router = str_or_default(settings, id("router"), defaultRouter);
|
||||
bool result;
|
||||
if (router == "router1") {
|
||||
result = router1(getCtx(), Router1Cfg(getCtx()));
|
||||
} else if (router == "router2") {
|
||||
router2(getCtx(), Router2Cfg(getCtx()));
|
||||
result = true;
|
||||
} else {
|
||||
log_error("iCE40 architecture does not support router '%s'\n", router.c_str());
|
||||
}
|
||||
getCtx()->settings[getCtx()->id("route")] = 1;
|
||||
archInfoToAttributes();
|
||||
return result;
|
||||
}
|
||||
|
||||
// ---------------------------------------------------------------
|
||||
|
||||
const std::vector<GraphicElement> &Arch::getDecalGraphics(DecalId decal) const
|
||||
{
|
||||
if (!decal_graphics.count(decal)) {
|
||||
std::cerr << "No decal named " << decal.str(this) << std::endl;
|
||||
log_error("No decal named %s!\n", decal.c_str(this));
|
||||
}
|
||||
return decal_graphics.at(decal);
|
||||
}
|
||||
|
||||
DecalXY Arch::getBelDecal(BelId bel) const { return bels.at(bel).decalxy; }
|
||||
|
||||
DecalXY Arch::getWireDecal(WireId wire) const { return wires.at(wire).decalxy; }
|
||||
|
||||
DecalXY Arch::getPipDecal(PipId pip) const { return pips.at(pip).decalxy; }
|
||||
|
||||
DecalXY Arch::getGroupDecal(GroupId group) const { return groups.at(group).decalxy; }
|
||||
|
||||
// ---------------------------------------------------------------
|
||||
|
||||
bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
|
||||
{
|
||||
if (!cellTiming.count(cell->name))
|
||||
return false;
|
||||
const auto &tmg = cellTiming.at(cell->name);
|
||||
auto fnd = tmg.combDelays.find(CellDelayKey{fromPort, toPort});
|
||||
if (fnd != tmg.combDelays.end()) {
|
||||
delay = fnd->second;
|
||||
return true;
|
||||
} else {
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
// Get the port class, also setting clockPort if applicable
|
||||
TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const
|
||||
{
|
||||
if (!cellTiming.count(cell->name))
|
||||
return TMG_IGNORE;
|
||||
const auto &tmg = cellTiming.at(cell->name);
|
||||
if (tmg.clockingInfo.count(port))
|
||||
clockInfoCount = int(tmg.clockingInfo.at(port).size());
|
||||
else
|
||||
clockInfoCount = 0;
|
||||
return get_or_default(tmg.portClasses, port, TMG_IGNORE);
|
||||
}
|
||||
|
||||
TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port, int index) const
|
||||
{
|
||||
NPNR_ASSERT(cellTiming.count(cell->name));
|
||||
const auto &tmg = cellTiming.at(cell->name);
|
||||
NPNR_ASSERT(tmg.clockingInfo.count(port));
|
||||
return tmg.clockingInfo.at(port).at(index);
|
||||
}
|
||||
|
||||
bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
|
||||
{
|
||||
std::vector<const CellInfo *> cells;
|
||||
cells.push_back(cell);
|
||||
Loc loc = getBelLocation(bel);
|
||||
for (auto tbel : getBelsByTile(loc.x, loc.y)) {
|
||||
if (tbel == bel)
|
||||
continue;
|
||||
CellInfo *bound = getBoundBelCell(tbel);
|
||||
if (bound != nullptr)
|
||||
cells.push_back(bound);
|
||||
}
|
||||
return cellsCompatible(cells.data(), int(cells.size()));
|
||||
}
|
||||
|
||||
bool Arch::isBelLocationValid(BelId bel) const
|
||||
{
|
||||
std::vector<const CellInfo *> cells;
|
||||
Loc loc = getBelLocation(bel);
|
||||
for (auto tbel : getBelsByTile(loc.x, loc.y)) {
|
||||
CellInfo *bound = getBoundBelCell(tbel);
|
||||
if (bound != nullptr)
|
||||
cells.push_back(bound);
|
||||
}
|
||||
return cellsCompatible(cells.data(), int(cells.size()));
|
||||
}
|
||||
|
||||
#ifdef WITH_HEAP
|
||||
const std::string Arch::defaultPlacer = "heap";
|
||||
#else
|
||||
const std::string Arch::defaultPlacer = "sa";
|
||||
#endif
|
||||
|
||||
const std::vector<std::string> Arch::availablePlacers = {"sa",
|
||||
#ifdef WITH_HEAP
|
||||
"heap"
|
||||
#endif
|
||||
};
|
||||
|
||||
const std::string Arch::defaultRouter = "router1";
|
||||
const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};
|
||||
|
||||
void Arch::assignArchInfo()
|
||||
{
|
||||
for (auto &cell : getCtx()->cells) {
|
||||
CellInfo *ci = cell.second.get();
|
||||
if (ci->type == id("GENERIC_SLICE")) {
|
||||
ci->is_slice = true;
|
||||
ci->slice_clk = get_net_or_empty(ci, id("CLK"));
|
||||
} else {
|
||||
ci->is_slice = false;
|
||||
}
|
||||
ci->user_group = int_or_default(ci->attrs, id("PACK_GROUP"), -1);
|
||||
}
|
||||
}
|
||||
|
||||
bool Arch::cellsCompatible(const CellInfo **cells, int count) const
|
||||
{
|
||||
const NetInfo *clk = nullptr;
|
||||
int group = -1;
|
||||
for (int i = 0; i < count; i++) {
|
||||
const CellInfo *ci = cells[i];
|
||||
if (ci->is_slice && ci->slice_clk != nullptr) {
|
||||
if (clk == nullptr)
|
||||
clk = ci->slice_clk;
|
||||
else if (clk != ci->slice_clk)
|
||||
return false;
|
||||
}
|
||||
if (ci->user_group != -1) {
|
||||
if (group == -1)
|
||||
group = ci->user_group;
|
||||
else if (group != ci->user_group)
|
||||
return false;
|
||||
}
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
302
machxo2/arch.h
Normal file
302
machxo2/arch.h
Normal file
@ -0,0 +1,302 @@
|
||||
/*
|
||||
* nextpnr -- Next Generation Place and Route
|
||||
*
|
||||
* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef NEXTPNR_H
|
||||
#error Include "arch.h" via "nextpnr.h" only.
|
||||
#endif
|
||||
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
struct ArchArgs
|
||||
{
|
||||
// Number of LUT inputs
|
||||
int K = 4;
|
||||
// y = mx + c relationship between distance and delay for interconnect
|
||||
// delay estimates
|
||||
double delayScale = 0.1, delayOffset = 0;
|
||||
};
|
||||
|
||||
struct WireInfo;
|
||||
|
||||
struct PipInfo
|
||||
{
|
||||
IdString name, type;
|
||||
std::map<IdString, std::string> attrs;
|
||||
NetInfo *bound_net;
|
||||
WireId srcWire, dstWire;
|
||||
DelayInfo delay;
|
||||
DecalXY decalxy;
|
||||
Loc loc;
|
||||
};
|
||||
|
||||
struct WireInfo
|
||||
{
|
||||
IdString name, type;
|
||||
std::map<IdString, std::string> attrs;
|
||||
NetInfo *bound_net;
|
||||
std::vector<PipId> downhill, uphill, aliases;
|
||||
BelPin uphill_bel_pin;
|
||||
std::vector<BelPin> downhill_bel_pins;
|
||||
std::vector<BelPin> bel_pins;
|
||||
DecalXY decalxy;
|
||||
int x, y;
|
||||
};
|
||||
|
||||
struct PinInfo
|
||||
{
|
||||
IdString name;
|
||||
WireId wire;
|
||||
PortType type;
|
||||
};
|
||||
|
||||
struct BelInfo
|
||||
{
|
||||
IdString name, type;
|
||||
std::map<IdString, std::string> attrs;
|
||||
CellInfo *bound_cell;
|
||||
std::unordered_map<IdString, PinInfo> pins;
|
||||
DecalXY decalxy;
|
||||
int x, y, z;
|
||||
bool gb;
|
||||
};
|
||||
|
||||
struct GroupInfo
|
||||
{
|
||||
IdString name;
|
||||
std::vector<BelId> bels;
|
||||
std::vector<WireId> wires;
|
||||
std::vector<PipId> pips;
|
||||
std::vector<GroupId> groups;
|
||||
DecalXY decalxy;
|
||||
};
|
||||
|
||||
struct CellDelayKey
|
||||
{
|
||||
IdString from, to;
|
||||
inline bool operator==(const CellDelayKey &other) const { return from == other.from && to == other.to; }
|
||||
};
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
namespace std {
|
||||
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX CellDelayKey>
|
||||
{
|
||||
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX CellDelayKey &dk) const noexcept
|
||||
{
|
||||
std::size_t seed = std::hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(dk.from);
|
||||
seed ^= std::hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(dk.to) + 0x9e3779b9 + (seed << 6) + (seed >> 2);
|
||||
return seed;
|
||||
}
|
||||
};
|
||||
} // namespace std
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
struct CellTiming
|
||||
{
|
||||
std::unordered_map<IdString, TimingPortClass> portClasses;
|
||||
std::unordered_map<CellDelayKey, DelayInfo> combDelays;
|
||||
std::unordered_map<IdString, std::vector<TimingClockingInfo>> clockingInfo;
|
||||
};
|
||||
|
||||
struct Arch : BaseCtx
|
||||
{
|
||||
std::string chipName;
|
||||
|
||||
std::unordered_map<IdString, WireInfo> wires;
|
||||
std::unordered_map<IdString, PipInfo> pips;
|
||||
std::unordered_map<IdString, BelInfo> bels;
|
||||
std::unordered_map<GroupId, GroupInfo> groups;
|
||||
|
||||
// These functions include useful errors if not found
|
||||
WireInfo &wire_info(IdString wire);
|
||||
PipInfo &pip_info(IdString wire);
|
||||
BelInfo &bel_info(IdString wire);
|
||||
|
||||
std::vector<IdString> bel_ids, wire_ids, pip_ids;
|
||||
|
||||
std::unordered_map<Loc, BelId> bel_by_loc;
|
||||
std::vector<std::vector<std::vector<BelId>>> bels_by_tile;
|
||||
|
||||
std::unordered_map<DecalId, std::vector<GraphicElement>> decal_graphics;
|
||||
|
||||
int gridDimX, gridDimY;
|
||||
std::vector<std::vector<int>> tileBelDimZ;
|
||||
std::vector<std::vector<int>> tilePipDimZ;
|
||||
|
||||
std::unordered_map<IdString, CellTiming> cellTiming;
|
||||
|
||||
void addWire(IdString name, IdString type, int x, int y);
|
||||
void addPip(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay, Loc loc);
|
||||
void addAlias(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay);
|
||||
|
||||
void addBel(IdString name, IdString type, Loc loc, bool gb);
|
||||
void addBelInput(IdString bel, IdString name, IdString wire);
|
||||
void addBelOutput(IdString bel, IdString name, IdString wire);
|
||||
void addBelInout(IdString bel, IdString name, IdString wire);
|
||||
|
||||
void addGroupBel(IdString group, IdString bel);
|
||||
void addGroupWire(IdString group, IdString wire);
|
||||
void addGroupPip(IdString group, IdString pip);
|
||||
void addGroupGroup(IdString group, IdString grp);
|
||||
|
||||
void addDecalGraphic(DecalId decal, const GraphicElement &graphic);
|
||||
void setWireDecal(WireId wire, DecalXY decalxy);
|
||||
void setPipDecal(PipId pip, DecalXY decalxy);
|
||||
void setBelDecal(BelId bel, DecalXY decalxy);
|
||||
void setGroupDecal(GroupId group, DecalXY decalxy);
|
||||
|
||||
void setWireAttr(IdString wire, IdString key, const std::string &value);
|
||||
void setPipAttr(IdString pip, IdString key, const std::string &value);
|
||||
void setBelAttr(IdString bel, IdString key, const std::string &value);
|
||||
|
||||
void setLutK(int K);
|
||||
void setDelayScaling(double scale, double offset);
|
||||
|
||||
void addCellTimingClock(IdString cell, IdString port);
|
||||
void addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayInfo delay);
|
||||
void addCellTimingSetupHold(IdString cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold);
|
||||
void addCellTimingClockToOut(IdString cell, IdString port, IdString clock, DelayInfo clktoq);
|
||||
|
||||
// ---------------------------------------------------------------
|
||||
// Common Arch API. Every arch must provide the following methods.
|
||||
|
||||
ArchArgs args;
|
||||
Arch(ArchArgs args);
|
||||
|
||||
std::string getChipName() const { return chipName; }
|
||||
|
||||
IdString archId() const { return id("generic"); }
|
||||
ArchArgs archArgs() const { return args; }
|
||||
IdString archArgsToId(ArchArgs args) const { return id("none"); }
|
||||
|
||||
int getGridDimX() const { return gridDimX; }
|
||||
int getGridDimY() const { return gridDimY; }
|
||||
int getTileBelDimZ(int x, int y) const { return tileBelDimZ[x][y]; }
|
||||
int getTilePipDimZ(int x, int y) const { return tilePipDimZ[x][y]; }
|
||||
|
||||
BelId getBelByName(IdString name) const;
|
||||
IdString getBelName(BelId bel) const;
|
||||
Loc getBelLocation(BelId bel) const;
|
||||
BelId getBelByLocation(Loc loc) const;
|
||||
const std::vector<BelId> &getBelsByTile(int x, int y) const;
|
||||
bool getBelGlobalBuf(BelId bel) const;
|
||||
uint32_t getBelChecksum(BelId bel) const;
|
||||
void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength);
|
||||
void unbindBel(BelId bel);
|
||||
bool checkBelAvail(BelId bel) const;
|
||||
CellInfo *getBoundBelCell(BelId bel) const;
|
||||
CellInfo *getConflictingBelCell(BelId bel) const;
|
||||
const std::vector<BelId> &getBels() const;
|
||||
IdString getBelType(BelId bel) const;
|
||||
const std::map<IdString, std::string> &getBelAttrs(BelId bel) const;
|
||||
WireId getBelPinWire(BelId bel, IdString pin) const;
|
||||
PortType getBelPinType(BelId bel, IdString pin) const;
|
||||
std::vector<IdString> getBelPins(BelId bel) const;
|
||||
|
||||
WireId getWireByName(IdString name) const;
|
||||
IdString getWireName(WireId wire) const;
|
||||
IdString getWireType(WireId wire) const;
|
||||
const std::map<IdString, std::string> &getWireAttrs(WireId wire) const;
|
||||
uint32_t getWireChecksum(WireId wire) const;
|
||||
void bindWire(WireId wire, NetInfo *net, PlaceStrength strength);
|
||||
void unbindWire(WireId wire);
|
||||
bool checkWireAvail(WireId wire) const;
|
||||
NetInfo *getBoundWireNet(WireId wire) const;
|
||||
WireId getConflictingWireWire(WireId wire) const { return wire; }
|
||||
NetInfo *getConflictingWireNet(WireId wire) const;
|
||||
DelayInfo getWireDelay(WireId wire) const { return DelayInfo(); }
|
||||
const std::vector<WireId> &getWires() const;
|
||||
const std::vector<BelPin> &getWireBelPins(WireId wire) const;
|
||||
|
||||
PipId getPipByName(IdString name) const;
|
||||
IdString getPipName(PipId pip) const;
|
||||
IdString getPipType(PipId pip) const;
|
||||
const std::map<IdString, std::string> &getPipAttrs(PipId pip) const;
|
||||
uint32_t getPipChecksum(PipId pip) const;
|
||||
void bindPip(PipId pip, NetInfo *net, PlaceStrength strength);
|
||||
void unbindPip(PipId pip);
|
||||
bool checkPipAvail(PipId pip) const;
|
||||
NetInfo *getBoundPipNet(PipId pip) const;
|
||||
WireId getConflictingPipWire(PipId pip) const;
|
||||
NetInfo *getConflictingPipNet(PipId pip) const;
|
||||
const std::vector<PipId> &getPips() const;
|
||||
Loc getPipLocation(PipId pip) const;
|
||||
WireId getPipSrcWire(PipId pip) const;
|
||||
WireId getPipDstWire(PipId pip) const;
|
||||
DelayInfo getPipDelay(PipId pip) const;
|
||||
const std::vector<PipId> &getPipsDownhill(WireId wire) const;
|
||||
const std::vector<PipId> &getPipsUphill(WireId wire) const;
|
||||
const std::vector<PipId> &getWireAliases(WireId wire) const;
|
||||
|
||||
GroupId getGroupByName(IdString name) const;
|
||||
IdString getGroupName(GroupId group) const;
|
||||
std::vector<GroupId> getGroups() const;
|
||||
const std::vector<BelId> &getGroupBels(GroupId group) const;
|
||||
const std::vector<WireId> &getGroupWires(GroupId group) const;
|
||||
const std::vector<PipId> &getGroupPips(GroupId group) const;
|
||||
const std::vector<GroupId> &getGroupGroups(GroupId group) const;
|
||||
|
||||
delay_t estimateDelay(WireId src, WireId dst) const;
|
||||
delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const;
|
||||
delay_t getDelayEpsilon() const { return 0.001; }
|
||||
delay_t getRipupDelayPenalty() const { return 0.015; }
|
||||
float getDelayNS(delay_t v) const { return v; }
|
||||
|
||||
DelayInfo getDelayFromNS(float ns) const
|
||||
{
|
||||
DelayInfo del;
|
||||
del.delay = ns;
|
||||
return del;
|
||||
}
|
||||
|
||||
uint32_t getDelayChecksum(delay_t v) const { return 0; }
|
||||
bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const;
|
||||
|
||||
ArcBounds getRouteBoundingBox(WireId src, WireId dst) const;
|
||||
|
||||
bool pack();
|
||||
bool place();
|
||||
bool route();
|
||||
|
||||
const std::vector<GraphicElement> &getDecalGraphics(DecalId decal) const;
|
||||
DecalXY getBelDecal(BelId bel) const;
|
||||
DecalXY getWireDecal(WireId wire) const;
|
||||
DecalXY getPipDecal(PipId pip) const;
|
||||
DecalXY getGroupDecal(GroupId group) const;
|
||||
|
||||
bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
|
||||
// Get the port class, also setting clockInfoCount to the number of TimingClockingInfos associated with a port
|
||||
TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const;
|
||||
// Get the TimingClockingInfo of a port
|
||||
TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const;
|
||||
|
||||
bool isValidBelForCell(CellInfo *cell, BelId bel) const;
|
||||
bool isBelLocationValid(BelId bel) const;
|
||||
|
||||
static const std::string defaultPlacer;
|
||||
static const std::vector<std::string> availablePlacers;
|
||||
static const std::string defaultRouter;
|
||||
static const std::vector<std::string> availableRouters;
|
||||
|
||||
// ---------------------------------------------------------------
|
||||
// Internal usage
|
||||
void assignArchInfo();
|
||||
bool cellsCompatible(const CellInfo **cells, int count) const;
|
||||
};
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
241
machxo2/arch_pybindings.cc
Normal file
241
machxo2/arch_pybindings.cc
Normal file
@ -0,0 +1,241 @@
|
||||
/*
|
||||
* nextpnr -- Next Generation Place and Route
|
||||
*
|
||||
* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
|
||||
* Copyright (C) 2018 David Shah <dave@ds0.me>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef NO_PYTHON
|
||||
|
||||
#include "arch_pybindings.h"
|
||||
#include "nextpnr.h"
|
||||
#include "pybindings.h"
|
||||
#include "pywrappers.h"
|
||||
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
namespace PythonConversion {
|
||||
template <> struct string_converter<const IdString &>
|
||||
{
|
||||
const IdString &from_str(Context *ctx, std::string name) { NPNR_ASSERT_FALSE("unsupported"); }
|
||||
|
||||
std::string to_str(Context *ctx, const IdString &id) { return id.str(ctx); }
|
||||
};
|
||||
} // namespace PythonConversion
|
||||
|
||||
void arch_wrap_python()
|
||||
{
|
||||
using namespace PythonConversion;
|
||||
|
||||
auto arch_cls = class_<Arch, Arch *, bases<BaseCtx>, boost::noncopyable>("Arch", init<ArchArgs>());
|
||||
|
||||
auto dxy_cls = class_<ContextualWrapper<DecalXY>>("DecalXY_", no_init);
|
||||
readwrite_wrapper<DecalXY, decltype(&DecalXY::decal), &DecalXY::decal, conv_to_str<DecalId>,
|
||||
conv_from_str<DecalId>>::def_wrap(dxy_cls, "decal");
|
||||
readwrite_wrapper<DecalXY, decltype(&DecalXY::x), &DecalXY::x, pass_through<float>, pass_through<float>>::def_wrap(
|
||||
dxy_cls, "x");
|
||||
readwrite_wrapper<DecalXY, decltype(&DecalXY::y), &DecalXY::y, pass_through<float>, pass_through<float>>::def_wrap(
|
||||
dxy_cls, "y");
|
||||
|
||||
auto ctx_cls = class_<Context, Context *, bases<Arch>, boost::noncopyable>("Context", no_init)
|
||||
.def("checksum", &Context::checksum)
|
||||
.def("pack", &Context::pack)
|
||||
.def("place", &Context::place)
|
||||
.def("route", &Context::route);
|
||||
|
||||
class_<BelPin>("BelPin").def_readwrite("bel", &BelPin::bel).def_readwrite("pin", &BelPin::pin);
|
||||
|
||||
class_<DelayInfo>("DelayInfo").def("maxDelay", &DelayInfo::maxDelay).def("minDelay", &DelayInfo::minDelay);
|
||||
|
||||
fn_wrapper_1a<Context, decltype(&Context::getBelType), &Context::getBelType, conv_to_str<IdString>,
|
||||
conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelType");
|
||||
fn_wrapper_1a<Context, decltype(&Context::checkBelAvail), &Context::checkBelAvail, pass_through<bool>,
|
||||
conv_from_str<BelId>>::def_wrap(ctx_cls, "checkBelAvail");
|
||||
fn_wrapper_1a<Context, decltype(&Context::getBelChecksum), &Context::getBelChecksum, pass_through<uint32_t>,
|
||||
conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelChecksum");
|
||||
fn_wrapper_3a_v<Context, decltype(&Context::bindBel), &Context::bindBel, conv_from_str<BelId>,
|
||||
addr_and_unwrap<CellInfo>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindBel");
|
||||
fn_wrapper_1a_v<Context, decltype(&Context::unbindBel), &Context::unbindBel, conv_from_str<BelId>>::def_wrap(
|
||||
ctx_cls, "unbindBel");
|
||||
fn_wrapper_1a<Context, decltype(&Context::getBoundBelCell), &Context::getBoundBelCell, deref_and_wrap<CellInfo>,
|
||||
conv_from_str<BelId>>::def_wrap(ctx_cls, "getBoundBelCell");
|
||||
fn_wrapper_1a<Context, decltype(&Context::getConflictingBelCell), &Context::getConflictingBelCell,
|
||||
deref_and_wrap<CellInfo>, conv_from_str<BelId>>::def_wrap(ctx_cls, "getConflictingBelCell");
|
||||
fn_wrapper_0a<Context, decltype(&Context::getBels), &Context::getBels,
|
||||
wrap_context<const std::vector<BelId> &>>::def_wrap(ctx_cls, "getBels");
|
||||
|
||||
fn_wrapper_2a<Context, decltype(&Context::getBelPinWire), &Context::getBelPinWire, conv_to_str<WireId>,
|
||||
conv_from_str<BelId>, conv_from_str<IdString>>::def_wrap(ctx_cls, "getBelPinWire");
|
||||
fn_wrapper_1a<Context, decltype(&Context::getWireBelPins), &Context::getWireBelPins,
|
||||
wrap_context<const std::vector<BelPin> &>, conv_from_str<WireId>>::def_wrap(ctx_cls,
|
||||
"getWireBelPins");
|
||||
|
||||
fn_wrapper_1a<Context, decltype(&Context::getWireChecksum), &Context::getWireChecksum, pass_through<uint32_t>,
|
||||
conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireChecksum");
|
||||
fn_wrapper_3a_v<Context, decltype(&Context::bindWire), &Context::bindWire, conv_from_str<WireId>,
|
||||
addr_and_unwrap<NetInfo>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindWire");
|
||||
fn_wrapper_1a_v<Context, decltype(&Context::unbindWire), &Context::unbindWire, conv_from_str<WireId>>::def_wrap(
|
||||
ctx_cls, "unbindWire");
|
||||
fn_wrapper_1a<Context, decltype(&Context::checkWireAvail), &Context::checkWireAvail, pass_through<bool>,
|
||||
conv_from_str<WireId>>::def_wrap(ctx_cls, "checkWireAvail");
|
||||
fn_wrapper_1a<Context, decltype(&Context::getBoundWireNet), &Context::getBoundWireNet, deref_and_wrap<NetInfo>,
|
||||
conv_from_str<WireId>>::def_wrap(ctx_cls, "getBoundWireNet");
|
||||
fn_wrapper_1a<Context, decltype(&Context::getConflictingWireNet), &Context::getConflictingWireNet,
|
||||
deref_and_wrap<NetInfo>, conv_from_str<WireId>>::def_wrap(ctx_cls, "getConflictingWireNet");
|
||||
|
||||
fn_wrapper_0a<Context, decltype(&Context::getWires), &Context::getWires,
|
||||
wrap_context<const std::vector<WireId> &>>::def_wrap(ctx_cls, "getWires");
|
||||
|
||||
fn_wrapper_0a<Context, decltype(&Context::getPips), &Context::getPips,
|
||||
wrap_context<const std::vector<PipId> &>>::def_wrap(ctx_cls, "getPips");
|
||||
fn_wrapper_1a<Context, decltype(&Context::getPipChecksum), &Context::getPipChecksum, pass_through<uint32_t>,
|
||||
conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipChecksum");
|
||||
fn_wrapper_3a_v<Context, decltype(&Context::bindPip), &Context::bindPip, conv_from_str<PipId>,
|
||||
addr_and_unwrap<NetInfo>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindPip");
|
||||
fn_wrapper_1a_v<Context, decltype(&Context::unbindPip), &Context::unbindPip, conv_from_str<PipId>>::def_wrap(
|
||||
ctx_cls, "unbindPip");
|
||||
fn_wrapper_1a<Context, decltype(&Context::checkPipAvail), &Context::checkPipAvail, pass_through<bool>,
|
||||
conv_from_str<PipId>>::def_wrap(ctx_cls, "checkPipAvail");
|
||||
fn_wrapper_1a<Context, decltype(&Context::getBoundPipNet), &Context::getBoundPipNet, deref_and_wrap<NetInfo>,
|
||||
conv_from_str<PipId>>::def_wrap(ctx_cls, "getBoundPipNet");
|
||||
fn_wrapper_1a<Context, decltype(&Context::getConflictingPipNet), &Context::getConflictingPipNet,
|
||||
deref_and_wrap<NetInfo>, conv_from_str<PipId>>::def_wrap(ctx_cls, "getConflictingPipNet");
|
||||
|
||||
fn_wrapper_1a<Context, decltype(&Context::getPipsDownhill), &Context::getPipsDownhill,
|
||||
wrap_context<const std::vector<PipId> &>, conv_from_str<WireId>>::def_wrap(ctx_cls,
|
||||
"getPipsDownhill");
|
||||
fn_wrapper_1a<Context, decltype(&Context::getPipsUphill), &Context::getPipsUphill,
|
||||
wrap_context<const std::vector<PipId> &>, conv_from_str<WireId>>::def_wrap(ctx_cls, "getPipsUphill");
|
||||
fn_wrapper_1a<Context, decltype(&Context::getWireAliases), &Context::getWireAliases,
|
||||
wrap_context<const std::vector<PipId> &>, conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireAliases");
|
||||
|
||||
fn_wrapper_1a<Context, decltype(&Context::getPipSrcWire), &Context::getPipSrcWire, conv_to_str<WireId>,
|
||||
conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipSrcWire");
|
||||
fn_wrapper_1a<Context, decltype(&Context::getPipDstWire), &Context::getPipDstWire, conv_to_str<WireId>,
|
||||
conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipDstWire");
|
||||
fn_wrapper_1a<Context, decltype(&Context::getPipDelay), &Context::getPipDelay, pass_through<DelayInfo>,
|
||||
conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipDelay");
|
||||
|
||||
fn_wrapper_1a<Context, decltype(&Context::getDelayFromNS), &Context::getDelayFromNS, pass_through<DelayInfo>,
|
||||
pass_through<double>>::def_wrap(ctx_cls, "getDelayFromNS");
|
||||
|
||||
fn_wrapper_0a<Context, decltype(&Context::getChipName), &Context::getChipName, pass_through<std::string>>::def_wrap(
|
||||
ctx_cls, "getChipName");
|
||||
fn_wrapper_0a<Context, decltype(&Context::archId), &Context::archId, conv_to_str<IdString>>::def_wrap(ctx_cls,
|
||||
"archId");
|
||||
|
||||
fn_wrapper_3a<Context, decltype(&Context::constructDecalXY), &Context::constructDecalXY, wrap_context<DecalXY>,
|
||||
conv_from_str<DecalId>, pass_through<float>, pass_through<float>>::def_wrap(ctx_cls, "DecalXY");
|
||||
|
||||
typedef std::unordered_map<IdString, std::unique_ptr<CellInfo>> CellMap;
|
||||
typedef std::unordered_map<IdString, std::unique_ptr<NetInfo>> NetMap;
|
||||
typedef std::unordered_map<IdString, HierarchicalCell> HierarchyMap;
|
||||
|
||||
readonly_wrapper<Context, decltype(&Context::cells), &Context::cells, wrap_context<CellMap &>>::def_wrap(ctx_cls,
|
||||
"cells");
|
||||
readonly_wrapper<Context, decltype(&Context::nets), &Context::nets, wrap_context<NetMap &>>::def_wrap(ctx_cls,
|
||||
"nets");
|
||||
|
||||
fn_wrapper_2a_v<Context, decltype(&Context::addClock), &Context::addClock, conv_from_str<IdString>,
|
||||
pass_through<float>>::def_wrap(ctx_cls, "addClock");
|
||||
|
||||
// Generic arch construction API
|
||||
fn_wrapper_4a_v<Context, decltype(&Context::addWire), &Context::addWire, conv_from_str<IdString>,
|
||||
conv_from_str<IdString>, pass_through<int>, pass_through<int>>::def_wrap(ctx_cls, "addWire",
|
||||
(arg("name"), "type", "x",
|
||||
"y"));
|
||||
fn_wrapper_6a_v<Context, decltype(&Context::addPip), &Context::addPip, conv_from_str<IdString>,
|
||||
conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>, pass_through<DelayInfo>,
|
||||
pass_through<Loc>>::def_wrap(ctx_cls, "addPip",
|
||||
(arg("name"), "type", "srcWire", "dstWire", "delay", "loc"));
|
||||
fn_wrapper_5a_v<Context, decltype(&Context::addAlias), &Context::addAlias, conv_from_str<IdString>,
|
||||
conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>,
|
||||
pass_through<DelayInfo>>::def_wrap(ctx_cls, "addAlias",
|
||||
(arg("name"), "type", "srcWire", "dstWire", "delay"));
|
||||
|
||||
fn_wrapper_4a_v<Context, decltype(&Context::addBel), &Context::addBel, conv_from_str<IdString>,
|
||||
conv_from_str<IdString>, pass_through<Loc>, pass_through<bool>>::def_wrap(ctx_cls, "addBel",
|
||||
(arg("name"), "type",
|
||||
"loc", "gb"));
|
||||
fn_wrapper_3a_v<Context, decltype(&Context::addBelInput), &Context::addBelInput, conv_from_str<IdString>,
|
||||
conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addBelInput",
|
||||
(arg("bel"), "name", "wire"));
|
||||
fn_wrapper_3a_v<Context, decltype(&Context::addBelOutput), &Context::addBelOutput, conv_from_str<IdString>,
|
||||
conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addBelOutput",
|
||||
(arg("bel"), "name", "wire"));
|
||||
fn_wrapper_3a_v<Context, decltype(&Context::addBelInout), &Context::addBelInout, conv_from_str<IdString>,
|
||||
conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addBelInout",
|
||||
(arg("bel"), "name", "wire"));
|
||||
|
||||
fn_wrapper_2a_v<Context, decltype(&Context::addGroupBel), &Context::addGroupBel, conv_from_str<IdString>,
|
||||
conv_from_str<IdString>>::def_wrap(ctx_cls, "addGroupBel", (arg("group"), "bel"));
|
||||
fn_wrapper_2a_v<Context, decltype(&Context::addGroupWire), &Context::addGroupWire, conv_from_str<IdString>,
|
||||
conv_from_str<IdString>>::def_wrap(ctx_cls, "addGroupWire", (arg("group"), "wire"));
|
||||
fn_wrapper_2a_v<Context, decltype(&Context::addGroupPip), &Context::addGroupPip, conv_from_str<IdString>,
|
||||
conv_from_str<IdString>>::def_wrap(ctx_cls, "addGroupPip", (arg("group"), "pip"));
|
||||
fn_wrapper_2a_v<Context, decltype(&Context::addGroupGroup), &Context::addGroupPip, conv_from_str<IdString>,
|
||||
conv_from_str<IdString>>::def_wrap(ctx_cls, "addGroupGroup", (arg("group"), "grp"));
|
||||
|
||||
fn_wrapper_2a_v<Context, decltype(&Context::addDecalGraphic), &Context::addDecalGraphic, conv_from_str<DecalId>,
|
||||
pass_through<GraphicElement>>::def_wrap(ctx_cls, "addDecalGraphic", (arg("decal"), "graphic"));
|
||||
fn_wrapper_2a_v<Context, decltype(&Context::setWireDecal), &Context::setWireDecal, conv_from_str<DecalId>,
|
||||
unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setWireDecal", (arg("wire"), "decalxy"));
|
||||
fn_wrapper_2a_v<Context, decltype(&Context::setPipDecal), &Context::setPipDecal, conv_from_str<DecalId>,
|
||||
unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setPipDecal", (arg("pip"), "decalxy"));
|
||||
fn_wrapper_2a_v<Context, decltype(&Context::setBelDecal), &Context::setBelDecal, conv_from_str<DecalId>,
|
||||
unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setBelDecal", (arg("bel"), "decalxy"));
|
||||
fn_wrapper_2a_v<Context, decltype(&Context::setGroupDecal), &Context::setGroupDecal, conv_from_str<DecalId>,
|
||||
unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setGroupDecal", (arg("group"), "decalxy"));
|
||||
|
||||
fn_wrapper_3a_v<Context, decltype(&Context::setWireAttr), &Context::setWireAttr, conv_from_str<DecalId>,
|
||||
conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setWireAttr",
|
||||
(arg("wire"), "key", "value"));
|
||||
fn_wrapper_3a_v<Context, decltype(&Context::setBelAttr), &Context::setBelAttr, conv_from_str<DecalId>,
|
||||
conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setBelAttr",
|
||||
(arg("bel"), "key", "value"));
|
||||
fn_wrapper_3a_v<Context, decltype(&Context::setPipAttr), &Context::setPipAttr, conv_from_str<DecalId>,
|
||||
conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setPipAttr",
|
||||
(arg("pip"), "key", "value"));
|
||||
|
||||
fn_wrapper_1a_v<Context, decltype(&Context::setLutK), &Context::setLutK, pass_through<int>>::def_wrap(
|
||||
ctx_cls, "setLutK", arg("K"));
|
||||
fn_wrapper_2a_v<Context, decltype(&Context::setDelayScaling), &Context::setDelayScaling, pass_through<double>,
|
||||
pass_through<double>>::def_wrap(ctx_cls, "setDelayScaling", (arg("scale"), "offset"));
|
||||
|
||||
fn_wrapper_2a_v<Context, decltype(&Context::addCellTimingClock), &Context::addCellTimingClock,
|
||||
conv_from_str<IdString>, conv_from_str<IdString>>::def_wrap(ctx_cls, "addCellTimingClock",
|
||||
(arg("cell"), "port"));
|
||||
fn_wrapper_4a_v<Context, decltype(&Context::addCellTimingDelay), &Context::addCellTimingDelay,
|
||||
conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>,
|
||||
pass_through<DelayInfo>>::def_wrap(ctx_cls, "addCellTimingDelay",
|
||||
(arg("cell"), "fromPort", "toPort", "delay"));
|
||||
fn_wrapper_5a_v<Context, decltype(&Context::addCellTimingSetupHold), &Context::addCellTimingSetupHold,
|
||||
conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>, pass_through<DelayInfo>,
|
||||
pass_through<DelayInfo>>::def_wrap(ctx_cls, "addCellTimingSetupHold",
|
||||
(arg("cell"), "port", "clock", "setup", "hold"));
|
||||
fn_wrapper_4a_v<Context, decltype(&Context::addCellTimingClockToOut), &Context::addCellTimingClockToOut,
|
||||
conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>,
|
||||
pass_through<DelayInfo>>::def_wrap(ctx_cls, "addCellTimingClockToOut",
|
||||
(arg("cell"), "port", "clock", "clktoq"));
|
||||
|
||||
WRAP_MAP_UPTR(CellMap, "IdCellMap");
|
||||
WRAP_MAP_UPTR(NetMap, "IdNetMap");
|
||||
WRAP_MAP(HierarchyMap, wrap_context<HierarchicalCell &>, "HierarchyMap");
|
||||
WRAP_VECTOR(const std::vector<IdString>, conv_to_str<IdString>);
|
||||
}
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
|
||||
#endif
|
||||
31
machxo2/arch_pybindings.h
Normal file
31
machxo2/arch_pybindings.h
Normal file
@ -0,0 +1,31 @@
|
||||
/*
|
||||
* nextpnr -- Next Generation Place and Route
|
||||
*
|
||||
* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
|
||||
* Copyright (C) 2018 David Shah <david@symbioticeda.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
#ifndef ARCH_PYBINDINGS_H
|
||||
#define ARCH_PYBINDINGS_H
|
||||
#ifndef NO_PYTHON
|
||||
|
||||
#include "nextpnr.h"
|
||||
#include "pybindings.h"
|
||||
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
#endif
|
||||
#endif
|
||||
72
machxo2/archdefs.h
Normal file
72
machxo2/archdefs.h
Normal file
@ -0,0 +1,72 @@
|
||||
/*
|
||||
* nextpnr -- Next Generation Place and Route
|
||||
*
|
||||
* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef NEXTPNR_H
|
||||
#error Include "archdefs.h" via "nextpnr.h" only.
|
||||
#endif
|
||||
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
typedef float delay_t;
|
||||
|
||||
struct DelayInfo
|
||||
{
|
||||
delay_t delay = 0;
|
||||
|
||||
delay_t minRaiseDelay() const { return delay; }
|
||||
delay_t maxRaiseDelay() const { return delay; }
|
||||
|
||||
delay_t minFallDelay() const { return delay; }
|
||||
delay_t maxFallDelay() const { return delay; }
|
||||
|
||||
delay_t minDelay() const { return delay; }
|
||||
delay_t maxDelay() const { return delay; }
|
||||
|
||||
DelayInfo operator+(const DelayInfo &other) const
|
||||
{
|
||||
DelayInfo ret;
|
||||
ret.delay = this->delay + other.delay;
|
||||
return ret;
|
||||
}
|
||||
};
|
||||
|
||||
typedef IdString BelId;
|
||||
typedef IdString WireId;
|
||||
typedef IdString PipId;
|
||||
typedef IdString GroupId;
|
||||
typedef IdString DecalId;
|
||||
|
||||
struct ArchNetInfo
|
||||
{
|
||||
};
|
||||
|
||||
struct NetInfo;
|
||||
|
||||
struct ArchCellInfo
|
||||
{
|
||||
// Custom grouping set via "PACK_GROUP" attribute. All cells with the same group
|
||||
// value may share a tile (-1 = don't care, default if not set)
|
||||
int user_group;
|
||||
// Is a slice type primitive
|
||||
bool is_slice;
|
||||
// Only packing rule for slice type primitives is a single clock per tile
|
||||
const NetInfo *slice_clk;
|
||||
};
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
147
machxo2/cells.cc
Normal file
147
machxo2/cells.cc
Normal file
@ -0,0 +1,147 @@
|
||||
/*
|
||||
* nextpnr -- Next Generation Place and Route
|
||||
*
|
||||
* Copyright (C) 2019 David Shah <david@symbioticeda.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "cells.h"
|
||||
#include "design_utils.h"
|
||||
#include "log.h"
|
||||
#include "util.h"
|
||||
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
void add_port(const Context *ctx, CellInfo *cell, std::string name, PortType dir)
|
||||
{
|
||||
IdString id = ctx->id(name);
|
||||
NPNR_ASSERT(cell->ports.count(id) == 0);
|
||||
cell->ports[id] = PortInfo{id, nullptr, dir};
|
||||
}
|
||||
|
||||
std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::string name)
|
||||
{
|
||||
static int auto_idx = 0;
|
||||
std::unique_ptr<CellInfo> new_cell = std::unique_ptr<CellInfo>(new CellInfo());
|
||||
if (name.empty()) {
|
||||
new_cell->name = ctx->id("$nextpnr_" + type.str(ctx) + "_" + std::to_string(auto_idx++));
|
||||
} else {
|
||||
new_cell->name = ctx->id(name);
|
||||
}
|
||||
new_cell->type = type;
|
||||
if (type == ctx->id("GENERIC_SLICE")) {
|
||||
new_cell->params[ctx->id("K")] = ctx->args.K;
|
||||
new_cell->params[ctx->id("INIT")] = 0;
|
||||
new_cell->params[ctx->id("FF_USED")] = 0;
|
||||
|
||||
for (int i = 0; i < ctx->args.K; i++)
|
||||
add_port(ctx, new_cell.get(), "I[" + std::to_string(i) + "]", PORT_IN);
|
||||
|
||||
add_port(ctx, new_cell.get(), "CLK", PORT_IN);
|
||||
|
||||
add_port(ctx, new_cell.get(), "F", PORT_OUT);
|
||||
add_port(ctx, new_cell.get(), "Q", PORT_OUT);
|
||||
} else if (type == ctx->id("GENERIC_IOB")) {
|
||||
new_cell->params[ctx->id("INPUT_USED")] = 0;
|
||||
new_cell->params[ctx->id("OUTPUT_USED")] = 0;
|
||||
new_cell->params[ctx->id("ENABLE_USED")] = 0;
|
||||
|
||||
add_port(ctx, new_cell.get(), "PAD", PORT_INOUT);
|
||||
add_port(ctx, new_cell.get(), "I", PORT_IN);
|
||||
add_port(ctx, new_cell.get(), "EN", PORT_IN);
|
||||
add_port(ctx, new_cell.get(), "O", PORT_OUT);
|
||||
} else {
|
||||
log_error("unable to create generic cell of type %s", type.c_str(ctx));
|
||||
}
|
||||
return new_cell;
|
||||
}
|
||||
|
||||
void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
|
||||
{
|
||||
lc->params[ctx->id("INIT")] = lut->params[ctx->id("INIT")];
|
||||
|
||||
int lut_k = int_or_default(lut->params, ctx->id("K"), 4);
|
||||
NPNR_ASSERT(lut_k <= ctx->args.K);
|
||||
|
||||
for (int i = 0; i < lut_k; i++) {
|
||||
IdString port = ctx->id("I[" + std::to_string(i) + "]");
|
||||
replace_port(lut, port, lc, port);
|
||||
}
|
||||
|
||||
if (no_dff) {
|
||||
lc->params[ctx->id("FF_USED")] = 0;
|
||||
replace_port(lut, ctx->id("Q"), lc, ctx->id("F"));
|
||||
}
|
||||
}
|
||||
|
||||
void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_lut)
|
||||
{
|
||||
lc->params[ctx->id("FF_USED")] = 1;
|
||||
replace_port(dff, ctx->id("CLK"), lc, ctx->id("CLK"));
|
||||
|
||||
if (pass_thru_lut) {
|
||||
// Fill LUT with alternating 10
|
||||
const int init_size = 1 << lc->params[ctx->id("K")].as_int64();
|
||||
std::string init;
|
||||
init.reserve(init_size);
|
||||
for (int i = 0; i < init_size; i += 2)
|
||||
init.append("10");
|
||||
lc->params[ctx->id("INIT")] = Property::from_string(init);
|
||||
|
||||
replace_port(dff, ctx->id("D"), lc, ctx->id("I[0]"));
|
||||
}
|
||||
|
||||
replace_port(dff, ctx->id("Q"), lc, ctx->id("Q"));
|
||||
}
|
||||
|
||||
void nxio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *iob, std::unordered_set<IdString> &todelete_cells)
|
||||
{
|
||||
if (nxio->type == ctx->id("$nextpnr_ibuf")) {
|
||||
iob->params[ctx->id("INPUT_USED")] = 1;
|
||||
replace_port(nxio, ctx->id("O"), iob, ctx->id("O"));
|
||||
} else if (nxio->type == ctx->id("$nextpnr_obuf")) {
|
||||
iob->params[ctx->id("OUTPUT_USED")] = 1;
|
||||
replace_port(nxio, ctx->id("I"), iob, ctx->id("I"));
|
||||
} else if (nxio->type == ctx->id("$nextpnr_iobuf")) {
|
||||
// N.B. tristate will be dealt with below
|
||||
iob->params[ctx->id("INPUT_USED")] = 1;
|
||||
iob->params[ctx->id("OUTPUT_USED")] = 1;
|
||||
replace_port(nxio, ctx->id("I"), iob, ctx->id("I"));
|
||||
replace_port(nxio, ctx->id("O"), iob, ctx->id("O"));
|
||||
} else {
|
||||
NPNR_ASSERT(false);
|
||||
}
|
||||
NetInfo *donet = iob->ports.at(ctx->id("I")).net;
|
||||
CellInfo *tbuf = net_driven_by(
|
||||
ctx, donet, [](const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("$_TBUF_"); },
|
||||
ctx->id("Y"));
|
||||
if (tbuf) {
|
||||
iob->params[ctx->id("ENABLE_USED")] = 1;
|
||||
replace_port(tbuf, ctx->id("A"), iob, ctx->id("I"));
|
||||
replace_port(tbuf, ctx->id("E"), iob, ctx->id("EN"));
|
||||
|
||||
if (donet->users.size() > 1) {
|
||||
for (auto user : donet->users)
|
||||
log_info(" remaining tristate user: %s.%s\n", user.cell->name.c_str(ctx), user.port.c_str(ctx));
|
||||
log_error("unsupported tristate IO pattern for IO buffer '%s', "
|
||||
"instantiate GENERIC_IOB manually to ensure correct behaviour\n",
|
||||
nxio->name.c_str(ctx));
|
||||
}
|
||||
ctx->nets.erase(donet->name);
|
||||
todelete_cells.insert(tbuf->name);
|
||||
}
|
||||
}
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
55
machxo2/cells.h
Normal file
55
machxo2/cells.h
Normal file
@ -0,0 +1,55 @@
|
||||
/*
|
||||
* nextpnr -- Next Generation Place and Route
|
||||
*
|
||||
* Copyright (C) 2019 David Shah <david@symbioticeda.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "nextpnr.h"
|
||||
|
||||
#ifndef GENERIC_CELLS_H
|
||||
#define GENERIC_CELLS_H
|
||||
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
// Create a generic arch cell and return it
|
||||
// Name will be automatically assigned if not specified
|
||||
std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::string name = "");
|
||||
|
||||
// Return true if a cell is a LUT
|
||||
inline bool is_lut(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("LUT"); }
|
||||
|
||||
// Return true if a cell is a flipflop
|
||||
inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("DFF"); }
|
||||
|
||||
inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("GENERIC_SLICE"); }
|
||||
|
||||
// Convert a LUT primitive to (part of) an GENERIC_SLICE, swapping ports
|
||||
// as needed. Set no_dff if a DFF is not being used, so that the output
|
||||
// can be reconnected
|
||||
void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff = true);
|
||||
|
||||
// Convert a DFF primitive to (part of) an GENERIC_SLICE, setting parameters
|
||||
// and reconnecting signals as necessary. If pass_thru_lut is True, the LUT will
|
||||
// be configured as pass through and D connected to I0, otherwise D will be
|
||||
// ignored
|
||||
void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_lut = false);
|
||||
|
||||
// Convert a nextpnr IO buffer to a GENERIC_IOB
|
||||
void nxio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *sbio, std::unordered_set<IdString> &todelete_cells);
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
|
||||
#endif
|
||||
6
machxo2/examples/.gitignore
vendored
Normal file
6
machxo2/examples/.gitignore
vendored
Normal file
@ -0,0 +1,6 @@
|
||||
blinky.fasm
|
||||
__pycache__
|
||||
*.pyc
|
||||
pnrblinky.v
|
||||
/blinky_simtest
|
||||
*.vcd
|
||||
15
machxo2/examples/README.md
Normal file
15
machxo2/examples/README.md
Normal file
@ -0,0 +1,15 @@
|
||||
# MachXO2 Architecture Example
|
||||
|
||||
This contains a simple example of the nextpnr machxo2 API. As time goes on,
|
||||
python scripts required as boilerplate will be removed.
|
||||
|
||||
- simple.py procedurally generates a simple FPGA architecture with IO at the edges,
|
||||
logic slices in all other tiles, and interconnect only between adjacent tiles
|
||||
|
||||
- simple_timing.py annotates cells with timing data (this is a separate script that must be run after packing)
|
||||
|
||||
- write_fasm.py uses the nextpnr Python API to write a FASM file for a design
|
||||
|
||||
- bitstream.py uses write_fasm.py to create a FASM ("FPGA assembly") file for the place-and-routed design
|
||||
|
||||
- Run simple.sh to build an example design on the FPGA above
|
||||
0
machxo2/examples/__init__.py
Normal file
0
machxo2/examples/__init__.py
Normal file
17
machxo2/examples/bitstream.py
Normal file
17
machxo2/examples/bitstream.py
Normal file
@ -0,0 +1,17 @@
|
||||
from write_fasm import *
|
||||
from simple_config import K
|
||||
|
||||
# Need to tell FASM generator how to write parameters
|
||||
# (celltype, parameter) -> ParameterConfig
|
||||
param_map = {
|
||||
("GENERIC_SLICE", "K"): ParameterConfig(write=False),
|
||||
("GENERIC_SLICE", "INIT"): ParameterConfig(write=True, numeric=True, width=2**K),
|
||||
("GENERIC_SLICE", "FF_USED"): ParameterConfig(write=True, numeric=True, width=1),
|
||||
|
||||
("GENERIC_IOB", "INPUT_USED"): ParameterConfig(write=True, numeric=True, width=1),
|
||||
("GENERIC_IOB", "OUTPUT_USED"): ParameterConfig(write=True, numeric=True, width=1),
|
||||
("GENERIC_IOB", "ENABLE_USED"): ParameterConfig(write=True, numeric=True, width=1),
|
||||
}
|
||||
|
||||
with open("blinky.fasm", "w") as f:
|
||||
write_fasm(ctx, param_map, f)
|
||||
12
machxo2/examples/blinky.v
Normal file
12
machxo2/examples/blinky.v
Normal file
@ -0,0 +1,12 @@
|
||||
module top(input clk, rst, output reg [7:0] leds);
|
||||
|
||||
reg [7:0] ctr;
|
||||
always @(posedge clk)
|
||||
if (rst)
|
||||
ctr <= 8'h00;
|
||||
else
|
||||
ctr <= ctr + 1'b1;
|
||||
|
||||
assign leds = ctr;
|
||||
|
||||
endmodule
|
||||
38
machxo2/examples/blinky_tb.v
Normal file
38
machxo2/examples/blinky_tb.v
Normal file
@ -0,0 +1,38 @@
|
||||
`timescale 1ns / 1ps
|
||||
module blinky_tb;
|
||||
|
||||
reg clk = 1'b0, rst = 1'b0;
|
||||
reg [7:0] ctr_gold = 8'h00;
|
||||
wire [7:0] ctr_gate;
|
||||
top dut_i(.clk(clk), .rst(rst), .leds(ctr_gate));
|
||||
|
||||
task oneclk;
|
||||
begin
|
||||
clk = 1'b1;
|
||||
#10;
|
||||
clk = 1'b0;
|
||||
#10;
|
||||
end
|
||||
endtask
|
||||
|
||||
initial begin
|
||||
$dumpfile("blinky_simtest.vcd");
|
||||
$dumpvars(0, blinky_tb);
|
||||
#100;
|
||||
rst = 1'b1;
|
||||
repeat (5) oneclk;
|
||||
#5
|
||||
rst = 1'b0;
|
||||
#5
|
||||
repeat (500) begin
|
||||
if (ctr_gold !== ctr_gate) begin
|
||||
$display("mismatch gold=%b gate=%b", ctr_gold, ctr_gate);
|
||||
$stop;
|
||||
end
|
||||
oneclk;
|
||||
ctr_gold = ctr_gold + 1'b1;
|
||||
end
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
77
machxo2/examples/simple.py
Normal file
77
machxo2/examples/simple.py
Normal file
@ -0,0 +1,77 @@
|
||||
from simple_config import *
|
||||
|
||||
def is_io(x, y):
|
||||
return x == 0 or x == X-1 or y == 0 or y == Y-1
|
||||
|
||||
for x in range(X):
|
||||
for y in range(Y):
|
||||
# Bel port wires
|
||||
for z in range(N):
|
||||
ctx.addWire(name="X%dY%dZ%d_CLK" % (x, y, z), type="BEL_CLK", x=x, y=y)
|
||||
ctx.addWire(name="X%dY%dZ%d_Q" % (x, y, z), type="BEL_Q", x=x, y=y)
|
||||
ctx.addWire(name="X%dY%dZ%d_F" % (x, y, z), type="BEL_F", x=x, y=y)
|
||||
for i in range(K):
|
||||
ctx.addWire(name="X%dY%dZ%d_I%d" % (x, y, z, i), type="BEL_I", x=x, y=y)
|
||||
# Local wires
|
||||
for l in range(Wl):
|
||||
ctx.addWire(name="X%dY%d_LOCAL%d" % (x, y, l), type="LOCAL", x=x, y=y)
|
||||
# Create bels
|
||||
if is_io(x, y):
|
||||
if x == y:
|
||||
continue
|
||||
for z in range(2):
|
||||
ctx.addBel(name="X%dY%d_IO%d" % (x, y, z), type="GENERIC_IOB", loc=Loc(x, y, z), gb=False)
|
||||
ctx.addBelInput(bel="X%dY%d_IO%d" % (x, y, z), name="I", wire="X%dY%dZ%d_I0" % (x, y, z))
|
||||
ctx.addBelInput(bel="X%dY%d_IO%d" % (x, y, z), name="EN", wire="X%dY%dZ%d_I1" % (x, y, z))
|
||||
ctx.addBelOutput(bel="X%dY%d_IO%d" % (x, y, z), name="O", wire="X%dY%dZ%d_Q" % (x, y, z))
|
||||
else:
|
||||
for z in range(N):
|
||||
ctx.addBel(name="X%dY%d_SLICE%d" % (x, y, z), type="GENERIC_SLICE", loc=Loc(x, y, z), gb=False)
|
||||
ctx.addBelInput(bel="X%dY%d_SLICE%d" % (x, y, z), name="CLK", wire="X%dY%dZ%d_CLK" % (x, y, z))
|
||||
for k in range(K):
|
||||
ctx.addBelInput(bel="X%dY%d_SLICE%d" % (x, y, z), name="I[%d]" % k, wire="X%dY%dZ%d_I%d" % (x, y, z, k))
|
||||
ctx.addBelOutput(bel="X%dY%d_SLICE%d" % (x, y, z), name="F", wire="X%dY%dZ%d_F" % (x, y, z))
|
||||
ctx.addBelOutput(bel="X%dY%d_SLICE%d" % (x, y, z), name="Q", wire="X%dY%dZ%d_Q" % (x, y, z))
|
||||
|
||||
for x in range(X):
|
||||
for y in range(Y):
|
||||
# Pips driving bel input wires
|
||||
# Bel input wires are driven by every Si'th local with an offset
|
||||
def create_input_pips(dst, offset, skip):
|
||||
for i in range(offset % skip, Wl, skip):
|
||||
src = "X%dY%d_LOCAL%d" % (x, y, i)
|
||||
ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="BEL_INPUT",
|
||||
srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0))
|
||||
for z in range(N):
|
||||
create_input_pips("X%dY%dZ%d_CLK" % (x, y, z), 0, Si)
|
||||
for k in range(K):
|
||||
create_input_pips("X%dY%dZ%d_I%d" % (x, y, z, k), k % Si, Si)
|
||||
|
||||
# Pips from bel outputs to locals
|
||||
def create_output_pips(dst, offset, skip):
|
||||
for i in range(offset % skip, N, skip):
|
||||
src = "X%dY%dZ%d_F" % (x, y, i)
|
||||
ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="BEL_OUTPUT",
|
||||
srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0))
|
||||
src = "X%dY%dZ%d_Q" % (x, y, i)
|
||||
ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="BEL_OUTPUT",
|
||||
srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0))
|
||||
# Pips from neighbour locals to locals
|
||||
def create_neighbour_pips(dst, nx, ny, offset, skip):
|
||||
if nx < 0 or nx >= X or ny < 0 or ny >= Y:
|
||||
return
|
||||
for i in range(offset % skip, Wl, skip):
|
||||
src = "X%dY%d_LOCAL%d" % (nx, ny, i)
|
||||
ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="NEIGHBOUR",
|
||||
srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0))
|
||||
for l in range(Wl):
|
||||
dst = "X%dY%d_LOCAL%d" % (x, y, l)
|
||||
create_output_pips(dst, l % Sq, Sq)
|
||||
create_neighbour_pips(dst, x-1, y-1, (l + 1) % Sl, Sl)
|
||||
create_neighbour_pips(dst, x-1, y, (l + 2) % Sl, Sl)
|
||||
create_neighbour_pips(dst, x-1, y+1, (l + 2) % Sl, Sl)
|
||||
create_neighbour_pips(dst, x, y-1, (l + 3) % Sl, Sl)
|
||||
create_neighbour_pips(dst, x, y+1, (l + 4) % Sl, Sl)
|
||||
create_neighbour_pips(dst, x+1, y-1, (l + 5) % Sl, Sl)
|
||||
create_neighbour_pips(dst, x+1, y, (l + 6) % Sl, Sl)
|
||||
create_neighbour_pips(dst, x+1, y+1, (l + 7) % Sl, Sl)
|
||||
5
machxo2/examples/simple.sh
Normal file
5
machxo2/examples/simple.sh
Normal file
@ -0,0 +1,5 @@
|
||||
#!/usr/bin/env bash
|
||||
set -ex
|
||||
yosys -p "tcl ../synth/synth_generic.tcl 4 blinky.json" blinky.v
|
||||
${NEXTPNR:-../../nextpnr-machxo2} --pre-pack simple.py --pre-place simple_timing.py --json blinky.json --post-route bitstream.py --write pnrblinky.json
|
||||
yosys -p "read_verilog -lib ../synth/prims.v; read_json pnrblinky.json; dump -o blinky.il; show -format png -prefix blinky"
|
||||
15
machxo2/examples/simple_config.py
Normal file
15
machxo2/examples/simple_config.py
Normal file
@ -0,0 +1,15 @@
|
||||
# Grid size including IOBs at edges
|
||||
X = 12
|
||||
Y = 12
|
||||
# SLICEs per tile
|
||||
N = 8
|
||||
# LUT input count
|
||||
K = 4
|
||||
# Number of local wires
|
||||
Wl = N*(K+1) + 8
|
||||
# 1/Fc for bel input wire pips
|
||||
Si = 4
|
||||
# 1/Fc for Q to local wire pips
|
||||
Sq = 4
|
||||
# ~1/Fc local to neighbour local wire pips
|
||||
Sl = 8
|
||||
13
machxo2/examples/simple_timing.py
Normal file
13
machxo2/examples/simple_timing.py
Normal file
@ -0,0 +1,13 @@
|
||||
for cname, cell in ctx.cells:
|
||||
if cell.type != "GENERIC_SLICE":
|
||||
continue
|
||||
if cname in ("$PACKER_GND", "$PACKER_VCC"):
|
||||
continue
|
||||
K = int(cell.params["K"])
|
||||
ctx.addCellTimingClock(cell=cname, port="CLK")
|
||||
for i in range(K):
|
||||
ctx.addCellTimingSetupHold(cell=cname, port="I[%d]" % i, clock="CLK",
|
||||
setup=ctx.getDelayFromNS(0.2), hold=ctx.getDelayFromNS(0))
|
||||
ctx.addCellTimingClockToOut(cell=cname, port="Q", clock="CLK", clktoq=ctx.getDelayFromNS(0.2))
|
||||
for i in range(K):
|
||||
ctx.addCellTimingDelay(cell=cname, fromPort="I[%d]" % i, toPort="F", delay=ctx.getDelayFromNS(0.2))
|
||||
7
machxo2/examples/simtest.sh
Normal file
7
machxo2/examples/simtest.sh
Normal file
@ -0,0 +1,7 @@
|
||||
#!/usr/bin/env bash
|
||||
set -ex
|
||||
yosys -p "tcl ../synth/synth_generic.tcl 4 blinky.json" blinky.v
|
||||
${NEXTPNR:-../../nextpnr-machxo2} --no-iobs --pre-pack simple.py --pre-place simple_timing.py --json blinky.json --post-route bitstream.py --write pnrblinky.json
|
||||
yosys -p "read_json pnrblinky.json; write_verilog -noattr -norename pnrblinky.v"
|
||||
iverilog -o blinky_simtest ../synth/prims.v blinky_tb.v pnrblinky.v
|
||||
vvp -N ./blinky_simtest
|
||||
51
machxo2/examples/write_fasm.py
Normal file
51
machxo2/examples/write_fasm.py
Normal file
@ -0,0 +1,51 @@
|
||||
from collections import namedtuple
|
||||
|
||||
"""
|
||||
write: set to True to enable writing this parameter to FASM
|
||||
|
||||
numeric: set to True to write this parameter as a bit array (width>1) or
|
||||
single bit (width==1) named after the parameter. Otherwise this
|
||||
parameter will be written as `name.value`
|
||||
|
||||
width: width of numeric parameter (ignored for non-numeric parameters)
|
||||
|
||||
alias: an alternative name for this parameter (parameter name used if alias
|
||||
is None)
|
||||
"""
|
||||
ParameterConfig = namedtuple('ParameterConfig', 'write numeric width alias')
|
||||
|
||||
# FIXME use defaults= once Python 3.7 is standard
|
||||
ParameterConfig.__new__.__defaults__ = (False, True, 1, None)
|
||||
|
||||
|
||||
"""
|
||||
Write a design as FASM
|
||||
|
||||
ctx: nextpnr context
|
||||
paramCfg: map from (celltype, parametername) -> ParameterConfig describing how to write parameters
|
||||
f: output file
|
||||
"""
|
||||
def write_fasm(ctx, paramCfg, f):
|
||||
for nname, net in sorted(ctx.nets, key=lambda x: str(x[1].name)):
|
||||
print("# Net %s" % nname, file=f)
|
||||
for wire, pip in sorted(net.wires, key=lambda x: str(x[1])):
|
||||
if pip.pip != "":
|
||||
print("%s" % pip.pip, file=f)
|
||||
print("", file=f)
|
||||
for cname, cell in sorted(ctx.cells, key=lambda x: str(x[1].name)):
|
||||
print("# Cell %s at %s" % (cname, cell.bel), file=f)
|
||||
for param, val in sorted(cell.params, key=lambda x: str(x)):
|
||||
cfg = paramCfg[(cell.type, param)]
|
||||
if not cfg.write:
|
||||
continue
|
||||
fasm_name = cfg.alias if cfg.alias is not None else param
|
||||
if cfg.numeric:
|
||||
if cfg.width == 1:
|
||||
if int(val) != 0:
|
||||
print("%s.%s" % (cell.bel, fasm_name), file=f)
|
||||
else:
|
||||
# Parameters with width >32 are direct binary, otherwise denary
|
||||
print("%s.%s[%d:0] = %d'b%s" % (cell.bel, fasm_name, cfg.width-1, cfg.width, val), file=f)
|
||||
else:
|
||||
print("%s.%s.%s" % (cell.bel, fasm_name, val), file=f)
|
||||
print("", file=f)
|
||||
0
machxo2/family.cmake
Normal file
0
machxo2/family.cmake
Normal file
75
machxo2/main.cc
Normal file
75
machxo2/main.cc
Normal file
@ -0,0 +1,75 @@
|
||||
/*
|
||||
* nextpnr -- Next Generation Place and Route
|
||||
*
|
||||
* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifdef MAIN_EXECUTABLE
|
||||
|
||||
#include <fstream>
|
||||
#include "command.h"
|
||||
#include "design_utils.h"
|
||||
#include "log.h"
|
||||
#include "timing.h"
|
||||
|
||||
USING_NEXTPNR_NAMESPACE
|
||||
|
||||
class GenericCommandHandler : public CommandHandler
|
||||
{
|
||||
public:
|
||||
GenericCommandHandler(int argc, char **argv);
|
||||
virtual ~GenericCommandHandler(){};
|
||||
std::unique_ptr<Context> createContext(std::unordered_map<std::string, Property> &values) override;
|
||||
void setupArchContext(Context *ctx) override{};
|
||||
void customBitstream(Context *ctx) override;
|
||||
|
||||
protected:
|
||||
po::options_description getArchOptions() override;
|
||||
};
|
||||
|
||||
GenericCommandHandler::GenericCommandHandler(int argc, char **argv) : CommandHandler(argc, argv) {}
|
||||
|
||||
po::options_description GenericCommandHandler::getArchOptions()
|
||||
{
|
||||
po::options_description specific("Architecture specific options");
|
||||
specific.add_options()("generic", "set device type to generic");
|
||||
specific.add_options()("no-iobs", "disable automatic IO buffer insertion");
|
||||
return specific;
|
||||
}
|
||||
|
||||
void GenericCommandHandler::customBitstream(Context *ctx) {}
|
||||
|
||||
std::unique_ptr<Context> GenericCommandHandler::createContext(std::unordered_map<std::string, Property> &values)
|
||||
{
|
||||
ArchArgs chipArgs;
|
||||
if (values.find("arch.name") != values.end()) {
|
||||
std::string arch_name = values["arch.name"].as_string();
|
||||
if (arch_name != "generic")
|
||||
log_error("Unsuported architecture '%s'.\n", arch_name.c_str());
|
||||
}
|
||||
auto ctx = std::unique_ptr<Context>(new Context(chipArgs));
|
||||
if (vm.count("no-iobs"))
|
||||
ctx->settings[ctx->id("disable_iobs")] = Property::State::S1;
|
||||
return ctx;
|
||||
}
|
||||
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
GenericCommandHandler handler(argc, argv);
|
||||
return handler.exec();
|
||||
}
|
||||
|
||||
#endif
|
||||
288
machxo2/pack.cc
Normal file
288
machxo2/pack.cc
Normal file
@ -0,0 +1,288 @@
|
||||
/*
|
||||
* nextpnr -- Next Generation Place and Route
|
||||
*
|
||||
* Copyright (C) 2018-19 David Shah <david@symbioticeda.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <algorithm>
|
||||
#include <iterator>
|
||||
#include <unordered_set>
|
||||
#include "cells.h"
|
||||
#include "design_utils.h"
|
||||
#include "log.h"
|
||||
#include "util.h"
|
||||
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
// Pack LUTs and LUT-FF pairs
|
||||
static void pack_lut_lutffs(Context *ctx)
|
||||
{
|
||||
log_info("Packing LUT-FFs..\n");
|
||||
|
||||
std::unordered_set<IdString> packed_cells;
|
||||
std::vector<std::unique_ptr<CellInfo>> new_cells;
|
||||
for (auto cell : sorted(ctx->cells)) {
|
||||
CellInfo *ci = cell.second;
|
||||
if (ctx->verbose)
|
||||
log_info("cell '%s' is of type '%s'\n", ci->name.c_str(ctx), ci->type.c_str(ctx));
|
||||
if (is_lut(ctx, ci)) {
|
||||
std::unique_ptr<CellInfo> packed =
|
||||
create_generic_cell(ctx, ctx->id("GENERIC_SLICE"), ci->name.str(ctx) + "_LC");
|
||||
std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(packed->attrs, packed->attrs.begin()));
|
||||
packed_cells.insert(ci->name);
|
||||
if (ctx->verbose)
|
||||
log_info("packed cell %s into %s\n", ci->name.c_str(ctx), packed->name.c_str(ctx));
|
||||
// See if we can pack into a DFF
|
||||
// TODO: LUT cascade
|
||||
NetInfo *o = ci->ports.at(ctx->id("Q")).net;
|
||||
CellInfo *dff = net_only_drives(ctx, o, is_ff, ctx->id("D"), true);
|
||||
auto lut_bel = ci->attrs.find(ctx->id("BEL"));
|
||||
bool packed_dff = false;
|
||||
if (dff) {
|
||||
if (ctx->verbose)
|
||||
log_info("found attached dff %s\n", dff->name.c_str(ctx));
|
||||
auto dff_bel = dff->attrs.find(ctx->id("BEL"));
|
||||
if (lut_bel != ci->attrs.end() && dff_bel != dff->attrs.end() && lut_bel->second != dff_bel->second) {
|
||||
// Locations don't match, can't pack
|
||||
} else {
|
||||
lut_to_lc(ctx, ci, packed.get(), false);
|
||||
dff_to_lc(ctx, dff, packed.get(), false);
|
||||
ctx->nets.erase(o->name);
|
||||
if (dff_bel != dff->attrs.end())
|
||||
packed->attrs[ctx->id("BEL")] = dff_bel->second;
|
||||
packed_cells.insert(dff->name);
|
||||
if (ctx->verbose)
|
||||
log_info("packed cell %s into %s\n", dff->name.c_str(ctx), packed->name.c_str(ctx));
|
||||
packed_dff = true;
|
||||
}
|
||||
}
|
||||
if (!packed_dff) {
|
||||
lut_to_lc(ctx, ci, packed.get(), true);
|
||||
}
|
||||
new_cells.push_back(std::move(packed));
|
||||
}
|
||||
}
|
||||
for (auto pcell : packed_cells) {
|
||||
ctx->cells.erase(pcell);
|
||||
}
|
||||
for (auto &ncell : new_cells) {
|
||||
ctx->cells[ncell->name] = std::move(ncell);
|
||||
}
|
||||
}
|
||||
|
||||
// Pack FFs not packed as LUTFFs
|
||||
static void pack_nonlut_ffs(Context *ctx)
|
||||
{
|
||||
log_info("Packing non-LUT FFs..\n");
|
||||
|
||||
std::unordered_set<IdString> packed_cells;
|
||||
std::vector<std::unique_ptr<CellInfo>> new_cells;
|
||||
|
||||
for (auto cell : sorted(ctx->cells)) {
|
||||
CellInfo *ci = cell.second;
|
||||
if (is_ff(ctx, ci)) {
|
||||
std::unique_ptr<CellInfo> packed =
|
||||
create_generic_cell(ctx, ctx->id("GENERIC_SLICE"), ci->name.str(ctx) + "_DFFLC");
|
||||
std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(packed->attrs, packed->attrs.begin()));
|
||||
if (ctx->verbose)
|
||||
log_info("packed cell %s into %s\n", ci->name.c_str(ctx), packed->name.c_str(ctx));
|
||||
packed_cells.insert(ci->name);
|
||||
dff_to_lc(ctx, ci, packed.get(), true);
|
||||
new_cells.push_back(std::move(packed));
|
||||
}
|
||||
}
|
||||
for (auto pcell : packed_cells) {
|
||||
ctx->cells.erase(pcell);
|
||||
}
|
||||
for (auto &ncell : new_cells) {
|
||||
ctx->cells[ncell->name] = std::move(ncell);
|
||||
}
|
||||
}
|
||||
|
||||
// Merge a net into a constant net
|
||||
static void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constnet, bool constval)
|
||||
{
|
||||
orig->driver.cell = nullptr;
|
||||
for (auto user : orig->users) {
|
||||
if (user.cell != nullptr) {
|
||||
CellInfo *uc = user.cell;
|
||||
if (ctx->verbose)
|
||||
log_info("%s user %s\n", orig->name.c_str(ctx), uc->name.c_str(ctx));
|
||||
if ((is_lut(ctx, uc) || is_lc(ctx, uc)) && (user.port.str(ctx).at(0) == 'I') && !constval) {
|
||||
uc->ports[user.port].net = nullptr;
|
||||
} else {
|
||||
uc->ports[user.port].net = constnet;
|
||||
constnet->users.push_back(user);
|
||||
}
|
||||
}
|
||||
}
|
||||
orig->users.clear();
|
||||
}
|
||||
|
||||
// Pack constants (simple implementation)
|
||||
static void pack_constants(Context *ctx)
|
||||
{
|
||||
log_info("Packing constants..\n");
|
||||
|
||||
std::unique_ptr<CellInfo> gnd_cell = create_generic_cell(ctx, ctx->id("GENERIC_SLICE"), "$PACKER_GND");
|
||||
gnd_cell->params[ctx->id("INIT")] = Property(0, 1 << ctx->args.K);
|
||||
std::unique_ptr<NetInfo> gnd_net = std::unique_ptr<NetInfo>(new NetInfo);
|
||||
gnd_net->name = ctx->id("$PACKER_GND_NET");
|
||||
gnd_net->driver.cell = gnd_cell.get();
|
||||
gnd_net->driver.port = ctx->id("F");
|
||||
gnd_cell->ports.at(ctx->id("F")).net = gnd_net.get();
|
||||
|
||||
std::unique_ptr<CellInfo> vcc_cell = create_generic_cell(ctx, ctx->id("GENERIC_SLICE"), "$PACKER_VCC");
|
||||
// Fill with 1s
|
||||
vcc_cell->params[ctx->id("INIT")] = Property(Property::S1).extract(0, (1 << ctx->args.K), Property::S1);
|
||||
std::unique_ptr<NetInfo> vcc_net = std::unique_ptr<NetInfo>(new NetInfo);
|
||||
vcc_net->name = ctx->id("$PACKER_VCC_NET");
|
||||
vcc_net->driver.cell = vcc_cell.get();
|
||||
vcc_net->driver.port = ctx->id("F");
|
||||
vcc_cell->ports.at(ctx->id("F")).net = vcc_net.get();
|
||||
|
||||
std::vector<IdString> dead_nets;
|
||||
|
||||
bool gnd_used = false;
|
||||
|
||||
for (auto net : sorted(ctx->nets)) {
|
||||
NetInfo *ni = net.second;
|
||||
if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("GND")) {
|
||||
IdString drv_cell = ni->driver.cell->name;
|
||||
set_net_constant(ctx, ni, gnd_net.get(), false);
|
||||
gnd_used = true;
|
||||
dead_nets.push_back(net.first);
|
||||
ctx->cells.erase(drv_cell);
|
||||
} else if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("VCC")) {
|
||||
IdString drv_cell = ni->driver.cell->name;
|
||||
set_net_constant(ctx, ni, vcc_net.get(), true);
|
||||
dead_nets.push_back(net.first);
|
||||
ctx->cells.erase(drv_cell);
|
||||
}
|
||||
}
|
||||
|
||||
if (gnd_used) {
|
||||
ctx->cells[gnd_cell->name] = std::move(gnd_cell);
|
||||
ctx->nets[gnd_net->name] = std::move(gnd_net);
|
||||
}
|
||||
// Vcc cell always inserted for now, as it may be needed during carry legalisation (TODO: trim later if actually
|
||||
// never used?)
|
||||
ctx->cells[vcc_cell->name] = std::move(vcc_cell);
|
||||
ctx->nets[vcc_net->name] = std::move(vcc_net);
|
||||
|
||||
for (auto dn : dead_nets) {
|
||||
ctx->nets.erase(dn);
|
||||
}
|
||||
}
|
||||
|
||||
static bool is_nextpnr_iob(Context *ctx, CellInfo *cell)
|
||||
{
|
||||
return cell->type == ctx->id("$nextpnr_ibuf") || cell->type == ctx->id("$nextpnr_obuf") ||
|
||||
cell->type == ctx->id("$nextpnr_iobuf");
|
||||
}
|
||||
|
||||
static bool is_generic_iob(const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("GENERIC_IOB"); }
|
||||
|
||||
// Pack IO buffers
|
||||
static void pack_io(Context *ctx)
|
||||
{
|
||||
std::unordered_set<IdString> packed_cells;
|
||||
std::unordered_set<IdString> delete_nets;
|
||||
|
||||
std::vector<std::unique_ptr<CellInfo>> new_cells;
|
||||
log_info("Packing IOs..\n");
|
||||
|
||||
for (auto cell : sorted(ctx->cells)) {
|
||||
CellInfo *ci = cell.second;
|
||||
if (is_nextpnr_iob(ctx, ci)) {
|
||||
CellInfo *iob = nullptr;
|
||||
if (ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) {
|
||||
iob = net_only_drives(ctx, ci->ports.at(ctx->id("O")).net, is_generic_iob, ctx->id("PAD"), true, ci);
|
||||
|
||||
} else if (ci->type == ctx->id("$nextpnr_obuf")) {
|
||||
NetInfo *net = ci->ports.at(ctx->id("I")).net;
|
||||
iob = net_only_drives(ctx, net, is_generic_iob, ctx->id("PAD"), true, ci);
|
||||
}
|
||||
if (iob != nullptr) {
|
||||
// Trivial case, GENERIC_IOB used. Just destroy the net and the
|
||||
// iobuf
|
||||
log_info("%s feeds GENERIC_IOB %s, removing %s %s.\n", ci->name.c_str(ctx), iob->name.c_str(ctx),
|
||||
ci->type.c_str(ctx), ci->name.c_str(ctx));
|
||||
NetInfo *net = iob->ports.at(ctx->id("PAD")).net;
|
||||
if (((ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) &&
|
||||
net->users.size() > 1) ||
|
||||
(ci->type == ctx->id("$nextpnr_obuf") && (net->users.size() > 2 || net->driver.cell != nullptr)))
|
||||
log_error("PAD of %s '%s' connected to more than a single top level IO.\n", iob->type.c_str(ctx),
|
||||
iob->name.c_str(ctx));
|
||||
|
||||
if (net != nullptr) {
|
||||
delete_nets.insert(net->name);
|
||||
iob->ports.at(ctx->id("PAD")).net = nullptr;
|
||||
}
|
||||
if (ci->type == ctx->id("$nextpnr_iobuf")) {
|
||||
NetInfo *net2 = ci->ports.at(ctx->id("I")).net;
|
||||
if (net2 != nullptr) {
|
||||
delete_nets.insert(net2->name);
|
||||
}
|
||||
}
|
||||
} else if (bool_or_default(ctx->settings, ctx->id("disable_iobs"))) {
|
||||
// No IO buffer insertion; just remove nextpnr_[io]buf
|
||||
for (auto &p : ci->ports)
|
||||
disconnect_port(ctx, ci, p.first);
|
||||
} else {
|
||||
// Create a GENERIC_IOB buffer
|
||||
std::unique_ptr<CellInfo> ice_cell =
|
||||
create_generic_cell(ctx, ctx->id("GENERIC_IOB"), ci->name.str(ctx) + "$iob");
|
||||
nxio_to_iob(ctx, ci, ice_cell.get(), packed_cells);
|
||||
new_cells.push_back(std::move(ice_cell));
|
||||
iob = new_cells.back().get();
|
||||
}
|
||||
packed_cells.insert(ci->name);
|
||||
if (iob != nullptr)
|
||||
std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(iob->attrs, iob->attrs.begin()));
|
||||
}
|
||||
}
|
||||
for (auto pcell : packed_cells) {
|
||||
ctx->cells.erase(pcell);
|
||||
}
|
||||
for (auto dnet : delete_nets) {
|
||||
ctx->nets.erase(dnet);
|
||||
}
|
||||
for (auto &ncell : new_cells) {
|
||||
ctx->cells[ncell->name] = std::move(ncell);
|
||||
}
|
||||
}
|
||||
|
||||
// Main pack function
|
||||
bool Arch::pack()
|
||||
{
|
||||
Context *ctx = getCtx();
|
||||
try {
|
||||
log_break();
|
||||
pack_constants(ctx);
|
||||
pack_io(ctx);
|
||||
pack_lut_lutffs(ctx);
|
||||
pack_nonlut_ffs(ctx);
|
||||
ctx->settings[ctx->id("pack")] = 1;
|
||||
ctx->assignArchInfo();
|
||||
log_info("Checksum: 0x%08x\n", ctx->checksum());
|
||||
return true;
|
||||
} catch (log_execution_error_exception) {
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
12
machxo2/synth/cells_map.v
Normal file
12
machxo2/synth/cells_map.v
Normal file
@ -0,0 +1,12 @@
|
||||
module \$lut (A, Y);
|
||||
parameter WIDTH = 0;
|
||||
parameter LUT = 0;
|
||||
input [WIDTH-1:0] A;
|
||||
output Y;
|
||||
|
||||
localparam rep = 1<<(`LUT_K-WIDTH);
|
||||
|
||||
LUT #(.K(`LUT_K), .INIT({rep{LUT}})) _TECHMAP_REPLACE_ (.I(A), .Q(Y));
|
||||
endmodule
|
||||
|
||||
module \$_DFF_P_ (input D, C, output Q); DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
|
||||
67
machxo2/synth/prims.v
Normal file
67
machxo2/synth/prims.v
Normal file
@ -0,0 +1,67 @@
|
||||
// LUT and DFF are combined to a GENERIC_SLICE
|
||||
|
||||
module LUT #(
|
||||
parameter K = 4,
|
||||
parameter [2**K-1:0] INIT = 0
|
||||
) (
|
||||
input [K-1:0] I,
|
||||
output Q
|
||||
);
|
||||
wire [K-1:0] I_pd;
|
||||
|
||||
genvar ii;
|
||||
generate
|
||||
for (ii = 0; ii < K; ii = ii + 1'b1)
|
||||
assign I_pd[ii] = (I[ii] === 1'bz) ? 1'b0 : I[ii];
|
||||
endgenerate
|
||||
|
||||
assign Q = INIT[I_pd];
|
||||
endmodule
|
||||
|
||||
module DFF (
|
||||
input CLK, D,
|
||||
output reg Q
|
||||
);
|
||||
initial Q = 1'b0;
|
||||
always @(posedge CLK)
|
||||
Q <= D;
|
||||
endmodule
|
||||
|
||||
module GENERIC_SLICE #(
|
||||
parameter K = 4,
|
||||
parameter [2**K-1:0] INIT = 0,
|
||||
parameter FF_USED = 1'b0
|
||||
) (
|
||||
input CLK,
|
||||
input [K-1:0] I,
|
||||
output F,
|
||||
output Q
|
||||
);
|
||||
wire f_wire;
|
||||
|
||||
LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(f_wire));
|
||||
|
||||
DFF dff_i(.CLK(CLK), .D(f_wire), .Q(Q));
|
||||
|
||||
assign F = f_wire;
|
||||
endmodule
|
||||
|
||||
module GENERIC_IOB #(
|
||||
parameter INPUT_USED = 1'b0,
|
||||
parameter OUTPUT_USED = 1'b0,
|
||||
parameter ENABLE_USED = 1'b0
|
||||
) (
|
||||
inout PAD,
|
||||
input I, EN,
|
||||
output O
|
||||
);
|
||||
generate if (OUTPUT_USED && ENABLE_USED)
|
||||
assign PAD = EN ? I : 1'bz;
|
||||
else if (OUTPUT_USED)
|
||||
assign PAD = I;
|
||||
endgenerate
|
||||
|
||||
generate if (INPUT_USED)
|
||||
assign O = PAD;
|
||||
endgenerate
|
||||
endmodule
|
||||
24
machxo2/synth/synth_machxo2.tcl
Normal file
24
machxo2/synth/synth_machxo2.tcl
Normal file
@ -0,0 +1,24 @@
|
||||
# Usage
|
||||
# tcl synth_generic.tcl {K} {out.json}
|
||||
|
||||
set LUT_K 4
|
||||
if {$argc > 0} { set LUT_K [lindex $argv 0] }
|
||||
yosys read_verilog -lib [file dirname [file normalize $argv0]]/prims.v
|
||||
yosys hierarchy -check
|
||||
yosys proc
|
||||
yosys flatten
|
||||
yosys tribuf -logic
|
||||
yosys deminout
|
||||
yosys synth -run coarse
|
||||
yosys memory_map
|
||||
yosys opt -full
|
||||
yosys techmap -map +/techmap.v
|
||||
yosys opt -fast
|
||||
yosys abc -lut $LUT_K -dress
|
||||
yosys clean
|
||||
yosys techmap -D LUT_K=$LUT_K -map [file dirname [file normalize $argv0]]/cells_map.v
|
||||
yosys clean
|
||||
yosys hierarchy -check
|
||||
yosys stat
|
||||
|
||||
if {$argc > 1} { yosys write_json [lindex $argv 1] }
|
||||
Loading…
Reference in New Issue
Block a user