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Merge pull request #1058 from YosysHQ/gatecat/bounds-refactor

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refactor: rename ArcBounds -> BoundingBox and use this in HeAP
This commit is contained in:
myrtle 2022-12-07 10:26:17 +01:00 committed by GitHub
commit 519011533a
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GPG Key ID: 4AEE18F83AFDEB23
27 changed files with 57 additions and 63 deletions
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4
common/kernel/arch_api.h
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@ -118,7 +118,7 @@ template <typename R> struct ArchAPI : BaseCtx
virtual uint32_t getDelayChecksum(delay_t v) const = 0;
virtual bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const = 0;
virtual delay_t estimateDelay(WireId src, WireId dst) const = 0;
virtual ArcBounds getRouteBoundingBox(WireId src, WireId dst) const = 0;
virtual BoundingBox getRouteBoundingBox(WireId src, WireId dst) const = 0;
// Decal methods
virtual typename R::DecalGfxRangeT getDecalGraphics(DecalId decal) const = 0;
virtual DecalXY getBelDecal(BelId bel) const = 0;
@ -141,7 +141,7 @@ template <typename R> struct ArchAPI : BaseCtx
virtual typename R::BucketBelRangeT getBelsInBucket(BelBucketId bucket) const = 0;
// Cluster methods
virtual CellInfo *getClusterRootCell(ClusterId cluster) const = 0;
virtual ArcBounds getClusterBounds(ClusterId cluster) const = 0;
virtual BoundingBox getClusterBounds(ClusterId cluster) const = 0;
virtual Loc getClusterOffset(const CellInfo *cell) const = 0;
virtual bool isClusterStrict(const CellInfo *cell) const = 0;
virtual bool getClusterPlacement(ClusterId cluster, BelId root_bel,

6
common/kernel/base_arch.h
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@ -377,10 +377,10 @@ template <typename R> struct BaseArch : ArchAPI<R>
// Cluster methods
virtual CellInfo *getClusterRootCell(ClusterId cluster) const override { return get_cluster_root(this, cluster); }
virtual ArcBounds getClusterBounds(ClusterId cluster) const override
virtual BoundingBox getClusterBounds(ClusterId cluster) const override
{
return if_using_basecluster<ArcBounds>(get_cluster_root(this, cluster), [](const BaseClusterInfo *cluster) {
ArcBounds bounds(0, 0, 0, 0);
return if_using_basecluster<BoundingBox>(get_cluster_root(this, cluster), [](const BaseClusterInfo *cluster) {
BoundingBox bounds(0, 0, 0, 0);
for (auto child : cluster->constr_children) {
if_using_basecluster<void>(child, [&](const BaseClusterInfo *child) {
bounds.x0 = std::min(bounds.x0, child->constr_x);

6
common/kernel/nextpnr_base_types.h
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@ -95,12 +95,12 @@ struct Loc
unsigned int hash() const { return mkhash(x, mkhash(y, z)); }
};
struct ArcBounds
struct BoundingBox
{
int x0 = -1, y0 = -1, x1 = -1, y1 = -1;
ArcBounds() {}
ArcBounds(int x0, int y0, int x1, int y1) : x0(x0), y0(y0), x1(x1), y1(y1){};
BoundingBox() {}
BoundingBox(int x0, int y0, int x1, int y1) : x0(x0), y0(y0), x1(x1), y1(y1){};
int distance(Loc loc) const
{

6
common/place/placer_heap.cc
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@ -377,12 +377,6 @@ class HeAPPlacer
TimingAnalyser tmg;
struct BoundingBox
{
// Actual bounding box
int x0 = 0, x1 = 0, y0 = 0, y1 = 0;
};
dict<IdString, BoundingBox> constraint_region_bounds;
// In some cases, we can't use bindBel because we allow overlap in the earlier stages. So we use this custom

30
common/route/router2.cc
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@ -51,7 +51,7 @@ struct Router2
struct PerArcData
{
WireId sink_wire;
ArcBounds bb;
BoundingBox bb;
bool routed = false;
};
@ -62,7 +62,7 @@ struct Router2
WireId src_wire;
dict<WireId, std::pair<PipId, int>> wires;
std::vector<std::vector<PerArcData>> arcs;
ArcBounds bb;
BoundingBox bb;
// Coordinates of the center of the net, used for the weight-to-average
int cx, cy, hpwl;
int total_route_us = 0;
@ -206,7 +206,7 @@ struct Router2
}
}
ArcBounds wire_loc = ctx->getRouteBoundingBox(wire, wire);
BoundingBox wire_loc = ctx->getRouteBoundingBox(wire, wire);
pwd.x = (wire_loc.x0 + wire_loc.x1) / 2;
pwd.y = (wire_loc.y0 + wire_loc.y1) / 2;
@ -249,7 +249,7 @@ struct Router2
};
};
bool hit_test_pip(ArcBounds &bb, Loc l) { return l.x >= bb.x0 && l.x <= bb.x1 && l.y >= bb.y0 && l.y <= bb.y1; }
bool hit_test_pip(BoundingBox &bb, Loc l) { return l.x >= bb.x0 && l.x <= bb.x1 && l.y >= bb.y0 && l.y <= bb.y1; }
double curr_cong_weight, hist_cong_weight, estimate_weight;
@ -269,7 +269,7 @@ struct Router2
std::vector<int> dirty_wires;
// Thread bounding box
ArcBounds bb;
BoundingBox bb;
DeterministicRNG rng;
@ -1217,7 +1217,7 @@ struct Router2
if (route_queue.size() < 200) {
ThreadContext st;
st.rng.rngseed(ctx->rng64());
st.bb = ArcBounds(0, 0, std::numeric_limits<int>::max(), std::numeric_limits<int>::max());
st.bb = BoundingBox(0, 0, std::numeric_limits<int>::max(), std::numeric_limits<int>::max());
for (size_t j = 0; j < route_queue.size(); j++) {
route_net(st, nets_by_udata[route_queue[j]], false);
}
@ -1234,19 +1234,19 @@ struct Router2
int le_y = mid_y;
int rs_y = mid_y;
// Set up thread bounding boxes
tcs.at(0).bb = ArcBounds(0, 0, mid_x, mid_y);
tcs.at(1).bb = ArcBounds(mid_x + 1, 0, std::numeric_limits<int>::max(), le_y);
tcs.at(2).bb = ArcBounds(0, mid_y + 1, mid_x, std::numeric_limits<int>::max());
tcs.at(0).bb = BoundingBox(0, 0, mid_x, mid_y);
tcs.at(1).bb = BoundingBox(mid_x + 1, 0, std::numeric_limits<int>::max(), le_y);
tcs.at(2).bb = BoundingBox(0, mid_y + 1, mid_x, std::numeric_limits<int>::max());
tcs.at(3).bb =
ArcBounds(mid_x + 1, mid_y + 1, std::numeric_limits<int>::max(), std::numeric_limits<int>::max());
BoundingBox(mid_x + 1, mid_y + 1, std::numeric_limits<int>::max(), std::numeric_limits<int>::max());
tcs.at(4).bb = ArcBounds(0, 0, std::numeric_limits<int>::max(), mid_y);
tcs.at(5).bb = ArcBounds(0, mid_y + 1, std::numeric_limits<int>::max(), std::numeric_limits<int>::max());
tcs.at(4).bb = BoundingBox(0, 0, std::numeric_limits<int>::max(), mid_y);
tcs.at(5).bb = BoundingBox(0, mid_y + 1, std::numeric_limits<int>::max(), std::numeric_limits<int>::max());
tcs.at(6).bb = ArcBounds(0, 0, mid_x, std::numeric_limits<int>::max());
tcs.at(7).bb = ArcBounds(mid_x + 1, 0, std::numeric_limits<int>::max(), std::numeric_limits<int>::max());
tcs.at(6).bb = BoundingBox(0, 0, mid_x, std::numeric_limits<int>::max());
tcs.at(7).bb = BoundingBox(mid_x + 1, 0, std::numeric_limits<int>::max(), std::numeric_limits<int>::max());
tcs.at(8).bb = ArcBounds(0, 0, std::numeric_limits<int>::max(), std::numeric_limits<int>::max());
tcs.at(8).bb = BoundingBox(0, 0, std::numeric_limits<int>::max(), std::numeric_limits<int>::max());
for (auto n : route_queue) {
auto &nd = nets.at(n);

4
docs/archapi.md
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@ -333,7 +333,7 @@ Get a list of all wires on the device.
Get a list of all bel pins attached to a given wire.
### ArcBounds getRouteBoundingBox(WireId src, WireId dst) const
### BoundingBox getRouteBoundingBox(WireId src, WireId dst) const
Get the bounding box required to route an arc, assuming an uncongested
chip. There may be significant performance impacts if routing regularly
@ -732,7 +732,7 @@ Cluster Methods
Gets the root cell of a cluster, which is used as a datum point when placing the cluster.
### ArcBounds getClusterBounds(ClusterId cluster) const
### BoundingBox getClusterBounds(ClusterId cluster) const
Gets an approximate bounding box of the cluster. This is intended for area allocation in the placer and is permitted to occasionally give incorrect estimates, for example due to irregularities in the fabric depending on cluster placement. `getClusterPlacement` should always be used to get exact locations.

4
ecp5/arch.cc
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@ -504,9 +504,9 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
(6 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5)));
}
ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
{
ArcBounds bb;
BoundingBox bb;
bb.x0 = src.location.x;
bb.y0 = src.location.y;

2
ecp5/arch.h
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@ -968,7 +968,7 @@ struct Arch : BaseArch<ArchRanges>
// -------------------------------------------------
delay_t estimateDelay(WireId src, WireId dst) const override;
ArcBounds getRouteBoundingBox(WireId src, WireId dst) const override;
BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override;
delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const override;
delay_t getDelayEpsilon() const override { return 20; }
delay_t getRipupDelayPenalty() const override;

2
fpga_interchange/arch.cc
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@ -730,7 +730,7 @@ std::vector<std::pair<IdString, std::string>> Arch::getBelAttrs(BelId bel) const
// -----------------------------------------------------------------------
ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
{
int dst_tile = dst.tile == -1 ? chip_info->nodes[dst.index].tile_wires[0].tile : dst.tile;
int src_tile = src.tile == -1 ? chip_info->nodes[src.index].tile_wires[0].tile : src.tile;

4
fpga_interchange/arch.h
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@ -701,7 +701,7 @@ struct Arch : ArchAPI<ArchRanges>
// -------------------------------------------------
delay_t estimateDelay(WireId src, WireId dst) const final;
delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const final;
ArcBounds getRouteBoundingBox(WireId src, WireId dst) const final;
BoundingBox getRouteBoundingBox(WireId src, WireId dst) const final;
delay_t getDelayEpsilon() const final { return 20; }
delay_t getRipupDelayPenalty() const final { return 120; }
float getDelayNS(delay_t v) const final { return v * 0.001; }
@ -896,7 +896,7 @@ struct Arch : ArchAPI<ArchRanges>
}
CellInfo *getClusterRootCell(ClusterId cluster) const override;
ArcBounds getClusterBounds(ClusterId cluster) const override;
BoundingBox getClusterBounds(ClusterId cluster) const override;
Loc getClusterOffset(const CellInfo *cell) const override;
bool isClusterStrict(const CellInfo *cell) const override;
bool normal_cluster_placement(const Context *, const Cluster &, const ClusterPOD &, CellInfo *, BelId,

4
fpga_interchange/arch_pack_clusters.cc
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@ -419,10 +419,10 @@ bool Arch::getClusterPlacement(ClusterId cluster, BelId root_bel,
}
}
ArcBounds Arch::getClusterBounds(ClusterId cluster) const
BoundingBox Arch::getClusterBounds(ClusterId cluster) const
{
// TODO: Implement this
ArcBounds bounds(0, 0, 0, 0);
BoundingBox bounds(0, 0, 0, 0);
return bounds;
}

4
fpga_interchange/cost_map.cc
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@ -184,7 +184,7 @@ static void assign_min_entry(delay_t *dst, const delay_t &src)
}
std::pair<delay_t, int> CostMap::get_nearby_cost_entry(const boost::multi_array<delay_t, 2> &matrix, int cx, int cy,
const ArcBounds &bounds)
const BoundingBox &bounds)
{
#ifdef DEBUG_FILL
log_info("Filling %d, %d within (%d, %d, %d, %d)\n", cx, cy, bounds.x0, bounds.y0, bounds.x1, bounds.y1);
@ -249,7 +249,7 @@ void CostMap::fill_holes(const Context *ctx, const TypeWirePair &type_pair, boos
// find missing cost entries and fill them in by copying a nearby cost entry
std::vector<std::tuple<unsigned, unsigned, delay_t>> missing;
bool couldnt_fill = false;
auto shifted_bounds = ArcBounds(0, 0, matrix.shape()[0] - 1, matrix.shape()[1] - 1);
auto shifted_bounds = BoundingBox(0, 0, matrix.shape()[0] - 1, matrix.shape()[1] - 1);
int max_fill = 0;
for (unsigned ix = 0; ix < matrix.shape()[0]; ix++) {
for (unsigned iy = 0; iy < matrix.shape()[1]; iy++) {

2
fpga_interchange/cost_map.h
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@ -58,7 +58,7 @@ class CostMap
delay_t delay_penality);
std::pair<delay_t, int> get_nearby_cost_entry(const boost::multi_array<delay_t, 2> &matrix, int cx, int cy,
const ArcBounds &bounds);
const BoundingBox &bounds);
delay_t get_penalty(const boost::multi_array<delay_t, 2> &matrix) const;
};

4
generic/arch.cc
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@ -548,11 +548,11 @@ delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdStr
bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; }
ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
{
if (uarch)
return uarch->getRouteBoundingBox(src, dst);
ArcBounds bb;
BoundingBox bb;
int src_x = wire_info(src).x;
int src_y = wire_info(src).y;

2
generic/arch.h
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@ -325,7 +325,7 @@ struct Arch : BaseArch<ArchRanges>
uint32_t getDelayChecksum(delay_t v) const override { return 0; }
bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override;
ArcBounds getRouteBoundingBox(WireId src, WireId dst) const override;
BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override;
bool pack() override;
bool place() override;

4
generic/viaduct_api.cc
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@ -61,9 +61,9 @@ delay_t ViaductAPI::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel,
int dy = abs(sink_loc.y - driver_loc.y);
return (dx + dy) * ctx->args.delayScale + ctx->args.delayOffset;
}
ArcBounds ViaductAPI::getRouteBoundingBox(WireId src, WireId dst) const
BoundingBox ViaductAPI::getRouteBoundingBox(WireId src, WireId dst) const
{
ArcBounds bb;
BoundingBox bb;
int src_x = ctx->wire_info(src).x;
int src_y = ctx->wire_info(src).y;
int dst_x = ctx->wire_info(dst).x;

2
generic/viaduct_api.h
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@ -82,7 +82,7 @@ struct ViaductAPI
// --- Route lookahead ---
virtual delay_t estimateDelay(WireId src, WireId dst) const;
virtual delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const;
virtual ArcBounds getRouteBoundingBox(WireId src, WireId dst) const;
virtual BoundingBox getRouteBoundingBox(WireId src, WireId dst) const;
// --- Flow hooks ---
virtual void pack(){}; // replaces the pack function

4
gowin/arch.cc
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@ -1909,9 +1909,9 @@ delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdStr
bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; }
ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
{
ArcBounds bb;
BoundingBox bb;
int src_x = wires.at(src).x;
int src_y = wires.at(src).y;

2
gowin/arch.h
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@ -447,7 +447,7 @@ struct Arch : BaseArch<ArchRanges>
uint32_t getDelayChecksum(delay_t v) const override { return 0; }
bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override;
ArcBounds getRouteBoundingBox(WireId src, WireId dst) const override;
BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override;
bool pack() override;
bool place() override;

4
ice40/arch.cc
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@ -1265,9 +1265,9 @@ void Arch::assignCellInfo(CellInfo *cell)
}
}
ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
{
ArcBounds bb;
BoundingBox bb;
int src_x = chip_info->wire_data[src.index].x;
int src_y = chip_info->wire_data[src.index].y;

2
ice40/arch.h
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@ -802,7 +802,7 @@ struct Arch : BaseArch<ArchRanges>
uint32_t getDelayChecksum(delay_t v) const override { return v; }
bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override;
ArcBounds getRouteBoundingBox(WireId src, WireId dst) const override;
BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override;
// -------------------------------------------------

4
machxo2/arch.cc
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@ -400,9 +400,9 @@ delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdStr
(0.01 + 0.01);
}
ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
{
ArcBounds bb;
BoundingBox bb;
bb.x0 = std::min(src.location.x, dst.location.x);
bb.y0 = std::min(src.location.y, dst.location.y);
bb.x1 = std::max(src.location.x, dst.location.x);

2
machxo2/arch.h
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@ -635,7 +635,7 @@ struct Arch : BaseArch<ArchRanges>
uint32_t getDelayChecksum(delay_t v) const override { return v; }
ArcBounds getRouteBoundingBox(WireId src, WireId dst) const override;
BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override;
// Flow
bool pack() override;

4
mistral/arch.cc
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@ -435,9 +435,9 @@ void Arch::assignArchInfo()
}
}
ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
{
ArcBounds bounds;
BoundingBox bounds;
int src_x = CycloneV::rn2x(src.node);
int src_y = CycloneV::rn2y(src.node);
int dst_x = CycloneV::rn2x(dst.node);

2
mistral/arch.h
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@ -425,7 +425,7 @@ struct Arch : BaseArch<ArchRanges>
delay_t getDelayFromNS(float ns) const override { return delay_t(ns * 1000.0f); };
uint32_t getDelayChecksum(delay_t v) const override { return v; };
ArcBounds getRouteBoundingBox(WireId src, WireId dst) const override;
BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override;
TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port,
int &clockInfoCount) const override; // delay.cc

4
nexus/arch.cc
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@ -702,9 +702,9 @@ delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdStr
bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; }
ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const
{
ArcBounds bb;
BoundingBox bb;
int src_x = src.tile % chip_info->width, src_y = src.tile / chip_info->width;
int dst_x = dst.tile % chip_info->width, dst_y = dst.tile / chip_info->width;

2
nexus/arch.h
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@ -1300,7 +1300,7 @@ struct Arch : BaseArch<ArchRanges>
delay_t getDelayFromNS(float ns) const override { return delay_t(ns * 1000); }
uint32_t getDelayChecksum(delay_t v) const override { return v; }
bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override;
ArcBounds getRouteBoundingBox(WireId src, WireId dst) const override;
BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override;
// for better DSP bounding boxes
void pre_routing();