Update README's with latest instructions and features.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Keith Rothman
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@ -36,28 +36,11 @@ library.
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The current implementation is missing essential features for place and route.
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As these features are added, this implementation will become more useful.
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- [ ] Placement constraints are unimplemented, meaning invalid or unroutable
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designs can be generated from the placer.
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- [ ] Logical netlist macro expansion is not implemented, meaning that any
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macro primitives are unplaceable. Common macro primitives examples are
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differential IO buffers (IBUFDS) and some LUT RAM (e.g. RAM64X1D).
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- [ ] Cell -> BEL pin mapping is not in place, meaning any primitives that
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have different BEL pins with respect to their cell pins will not be
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routable.
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- [ ] Nextpnr only allows for cell -> BEL pin maps that are 1 to 1. The
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FPGA interchange accommodates cell -> BEL pin maps that include 1 to
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many relationships for sinks. A common primitives that uses 1 to many
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maps are the RAMB18E1.
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- [ ] The router lookahead is missing, meaning that router runtime
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performance will be terrible.
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- [ ] Physical netlist backend is missing, so even if
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`nextpnr-fpga_interchange` completes successfully, there is no way to
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generate output that can be consumed by downstream tools.
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- [ ] XDC parsing and port constraints are unimplemented, so IO pins cannot
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be fixed. The chipdb BBA output is also missing package pin data, so
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only site constraints are currently possible. Eventually the chipdb BBA
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should also include package pin data to allow for ports to be bound to
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package pins.
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- [ ] The routing graph that is currently emitted does not have ground and
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VCC networks, so all signals must currently be tied to an IO signal.
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Site pins being tied to constants also needs handling so that site
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@ -72,6 +55,10 @@ As these features are added, this implementation will become more useful.
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database, so it is also currently missing from the FPGA interchange
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architecture. Once timing information is added to the device database
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schema, it needs to be added to the architecture.
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- [ ] Implemented site router lacks important features for tight packing,
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namely LUT rotation. Also the current site router is relatively
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untested, so legal configurations may be rejected and illegal
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configurations may be accepted.
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#### FPGA interchange fabrics
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@ -80,6 +67,48 @@ device database generator, via [RapidWright](https://github.com/Xilinx/RapidWrig
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##### Artix 35T example
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Install capnproto if not already installed:
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```
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# Or equivalent for your local system.
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sudo apt-get install capnproto libcapnp-dev
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```
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Install capnproto-java if not already installed:
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```
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git clone https://github.com/capnproto/capnproto-java.git
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cd capnproto-java
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make
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sudo make install
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```
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##### Makefile-driven BBA creation
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In `${NEXTPNR_DIR}/fpga_interchange/examples/create_bba` is a Makefile that
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should compile nextpnr and create a Xilinx A35 chipdb if java, capnproto and
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capnproto-java are installed.
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Instructions:
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```
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cd ${NEXTPNR_DIR}/fpga_interchange/examples/create_bba
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make
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```
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This will create a virtual env in
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`${NEXTPNR_DIR}/fpga_interchange/examples/create_bba/build/env` that has the
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python-fpga-interchange library installed. Before running the design examples,
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enter the virtual env, e.g.:
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```
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source ${NEXTPNR_DIR}/fpga_interchange/examples/create_bba/build/env/bin/activate
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```
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The chipdb will be written to `${NEXTPNR_DIR}/fpga_interchange/examples/create_bba/build/xc7a35.bin`
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once completed.
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##### Manual BBA creation
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This covers the manual set of steps to create a Xilinx A35 chipdb.
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Download RapidWright and generate the device database.
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```
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# FIXME: Use main branch once interchange branch is merged.
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@ -95,7 +124,11 @@ mv rapidwright-api-lib-2020.2.1_update1.jar jars/rapidwright-api-lib-2020.2.0.ja
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./scripts/invoke_rapidwright.sh com.xilinx.rapidwright.interchange.DeviceResourcesExample xc7a35tcpg236-1
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export RAPIDWRIGHT_PATH=$(pwd)
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export INTERCHANGE_DIR=$(pwd)/interchange
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```
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Set `INTERCHANGE_DIR` to point to 3rdparty/fpga-interchange-schema:
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```
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export INTERCHANGE_DIR=$(NEXTPNR_DIR)/3rdparty/fpga-interchange-schema/interchange
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```
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Install python FPGA interchange library.
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@ -130,7 +163,8 @@ Generate nextpnr BBA and constids.inc from device database:
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python3 -mfpga_interchange.nextpnr_emit \
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--schema_dir ${INTERCHANGE_DIR} \
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--output_dir ${NEXTPNR_DIR}/fpga_interchange/ \
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--device xc7a35tcpg236-1_constraints_luts.device
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--bel_bucket_seeds test_data/series7_bel_buckets.yaml \
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--device xc7a35tcpg236-1_constraints_luts.device \
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```
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Build nextpnr:
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@ -1,6 +1,6 @@
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NEXTPNR_PATH := $(realpath ../../..)
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NEXTPNR_BIN := $(NEXTPNR_PATH)/build/nextpnr-fpga_interchange
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BBA_PATH := $(realpath ..)/create_bba/build/xc7a35tcpg236-1.bin
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BBA_PATH := $(realpath ..)/create_bba/build/xc7a35.bin
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RAPIDWRIGHT_PATH := $(realpath ..)/create_bba/build/RapidWright
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INTERCHANGE_PATH := $(realpath ..)/create_bba/build/fpga-interchange-schema/interchange
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40
fpga_interchange/examples/create_bba/README.md
Normal file
40
fpga_interchange/examples/create_bba/README.md
Normal file
@ -0,0 +1,40 @@
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## Makefile-driven BBA creation
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This Makefile will generate a Xilinx A35 chipdb if java, capnproto and
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capnproto-java are installed.
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### Installing dependencies
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Install java and javac if not already installed:
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```
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# Or equivalent for your local system.
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sudo apt-get install openjdk-10-jdk
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```
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Install capnproto if not already installed:
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```
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# Or equivalent for your local system.
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sudo apt-get install capnproto libcapnp-dev
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```
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Install capnproto-java if not already installed:
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```
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git clone https://github.com/capnproto/capnproto-java.git
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cd capnproto-java
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make
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sudo make install
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```
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### Instructions
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Once dependencies are installed, just run "make". This should download
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remaining dependencies and build the chipdb and build nextpnr if not built.
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#### Re-building the chipdb
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```
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# Remove the text BBA
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rm build/nextpnr/fpga_interchange/chipdb.bba
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# Build the BBA
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make
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```
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