Improved delay estimator
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@ -5,6 +5,11 @@ yosys blinky.ys
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xdl -xdl2ncd blinky.xdl
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bitgen -w blinky.ncd -g UnconstrainedPins:Allow
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trce blinky.ncd -v 10
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netgen -ofmt verilog -w blinky.ncd blinky_chip.v -tm blinky
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iverilog -o blinky_tb blinky_chip.v blinky_tb.v -y/opt/Xilinx/14.7/ISE_DS/ISE/verilog/src/simprims/ -insert_glbl true
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vvp -N ./blinky_tb
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#netgen -ofmt verilog -w blinky.ncd blinky_chip.v -tm blinky -insert_glbl true
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#iverilog -o blinky_tb blinky_chip.v blinky_tb.v -y/opt/Xilinx/14.7/ISE_DS/ISE/verilog/src/simprims/
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#vvp -N ./blinky_tb
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#xdl -xdl2ncd blinky.xdl -nopips blinky_map.ncd
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#par -w blinky_map.ncd blinky_par.ncd blinky.pcf
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#bitgen -w blinky_par.ncd -g UnconstrainedPins:Allow
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46
xc7/delay.cc
46
xc7/delay.cc
@ -104,8 +104,27 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
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const auto &src_info = torc_info->tiles.getTileInfo(src_tw.getTileIndex());
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const auto &dst_tw = torc_info->wire_to_tilewire[dst.index];
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const auto &dst_info = torc_info->tiles.getTileInfo(dst_tw.getTileIndex());
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return 100 * (abs(src_info.getCol() - dst_info.getCol()) + abs(src_info.getRow() - dst_info.getRow()));
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auto abs_delta_x = abs(src_info.getCol() - dst_info.getCol());
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auto abs_delta_y = abs(src_info.getRow() - dst_info.getRow());
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#if 1
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auto div_LH = std::div(abs_delta_x, 12);
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auto div_LV = std::div(abs_delta_y, 18);
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auto div_LVB = std::div(div_LV.rem, 12);
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auto div_H6 = std::div(div_LH.rem, 6);
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auto div_V6 = std::div(div_LVB.rem, 6);
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auto div_H4 = std::div(div_H6.rem, 4);
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auto div_V4 = std::div(div_V6.rem, 4);
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auto div_H2 = std::div(div_H4.rem, 2);
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auto div_V2 = std::div(div_V4.rem, 2);
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auto num_H1 = div_H2.rem;
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auto num_V1 = div_V2.rem;
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return div_LH.quot * 360/2 + div_LVB.quot * 300 + div_LV.quot * 350
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+ (div_H6.quot + div_H4.quot) * 210/2 + (div_V6.quot + div_V4.quot) * 210
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+ div_H2.quot * 170/2 + div_V2.quot * 170
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+ num_H1 * 150/2 + num_V1 * 150;
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#else
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return std::max(150, 33 * abs_delta_x + 66 * abs_delta_y);
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#endif
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}
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delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
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@ -113,8 +132,27 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
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const auto &driver = net_info->driver;
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auto driver_loc = getBelLocation(driver.cell->bel);
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auto sink_loc = getBelLocation(sink.cell->bel);
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return 100 * (abs(driver_loc.x - sink_loc.x) + abs(driver_loc.y - sink_loc.y));
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auto abs_delta_x = abs(driver_loc.x - sink_loc.x);
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auto abs_delta_y = abs(driver_loc.y - sink_loc.y);
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#if 1
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auto div_LH = std::div(abs_delta_x, 12);
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auto div_LV = std::div(abs_delta_y, 18);
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auto div_LVB = std::div(div_LV.rem, 12);
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auto div_H6 = std::div(div_LH.rem, 6);
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auto div_V6 = std::div(div_LVB.rem, 6);
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auto div_H4 = std::div(div_H6.rem, 4);
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auto div_V4 = std::div(div_V6.rem, 4);
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auto div_H2 = std::div(div_H4.rem, 2);
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auto div_V2 = std::div(div_V4.rem, 2);
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auto num_H1 = div_H2.rem;
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auto num_V1 = div_V2.rem;
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return div_LH.quot * 360/2 + div_LVB.quot * 300 + div_LV.quot * 350
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+ (div_H6.quot + div_H4.quot) * 210/2 + (div_V6.quot + div_V4.quot) * 210
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+ div_H2.quot * 170/2 + div_V2.quot * 170
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+ num_H1 * 150/2 + num_V1 * 150;
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#else
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return std::max(150, 33 * abs_delta_x + 66 * abs_delta_y);
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#endif
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}
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NEXTPNR_NAMESPACE_END
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