timing: Add Fmax printing for debugging

Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-03-02 10:54:33 +00:00
parent 16e7bba87b
commit 541376f8cc
2 changed files with 23 additions and 0 deletions

View File

@ -39,6 +39,7 @@ void TimingAnalyser::setup()
reset_times();
walk_forward();
walk_backward();
print_fmax();
}
void TimingAnalyser::init_ports()
@ -386,6 +387,26 @@ void TimingAnalyser::walk_backward()
}
}
void TimingAnalyser::print_fmax()
{
// Temporary testing code for comparison only
std::unordered_map<int, double> domain_fmax;
for (auto p : topological_order) {
auto &pd = ports.at(p);
for (auto &req : pd.required) {
if (pd.arrival.count(req.first)) {
auto &arr = pd.arrival.at(req.first);
double fmax = 1000.0 / (arr.value.maxDelay() - req.second.value.minDelay());
if (!domain_fmax.count(req.first) || domain_fmax.at(req.first) > fmax)
domain_fmax[req.first] = fmax;
}
}
}
for (auto &fm : domain_fmax) {
log_info("Domain %s Worst Fmax %.02f\n", ctx->nameOf(domains.at(fm.first).key.clock), fm.second);
}
}
domain_id_t TimingAnalyser::domain_id(IdString cell, IdString clock_port, ClockEdge edge)
{
return domain_id(ctx->cells.at(cell)->ports.at(clock_port).net, edge);

View File

@ -140,6 +140,8 @@ struct TimingAnalyser
void walk_forward();
void walk_backward();
void print_fmax();
const DelayPair init_delay{std::numeric_limits<delay_t>::max(), std::numeric_limits<delay_t>::lowest()};
// Set arrival/required times if more/less than the current value