From 54b2045726fc3fe77857c05c81a5ab77e98ba851 Mon Sep 17 00:00:00 2001 From: gatecat Date: Tue, 20 Jun 2023 10:58:18 +0200 Subject: [PATCH] clangformat Signed-off-by: gatecat --- common/kernel/timing.cc | 16 ++++++++-------- common/place/placer1.cc | 2 +- common/route/router2.cc | 10 ++++++++-- gowin/pack.cc | 9 +++++---- mistral/delay.cc | 3 +-- mistral/pack.cc | 12 ++++++++---- 6 files changed, 31 insertions(+), 21 deletions(-) diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc index 6a6ac2c1..6ef227dc 100644 --- a/common/kernel/timing.cc +++ b/common/kernel/timing.cc @@ -30,7 +30,8 @@ NEXTPNR_NAMESPACE_BEGIN namespace { -std::string clock_event_name(const Context *ctx, ClockDomainKey &dom) { +std::string clock_event_name(const Context *ctx, ClockDomainKey &dom) +{ std::string value; if (dom.is_async()) value = ""; @@ -41,7 +42,8 @@ std::string clock_event_name(const Context *ctx, ClockDomainKey &dom) { } } // namespace -TimingAnalyser::TimingAnalyser(Context *ctx) : ctx(ctx) { +TimingAnalyser::TimingAnalyser(Context *ctx) : ctx(ctx) +{ ClockDomainKey key{IdString(), ClockEdge::RISING_EDGE}; domain_to_id.emplace(key, 0); domains.emplace_back(key); @@ -115,7 +117,7 @@ void TimingAnalyser::get_cell_delays() } // asynchronous endpoint else if (cls == TMG_ENDPOINT) { - pd.cell_arcs.emplace_back(CellArc::ENDPOINT, async_clk_key.key.clock, DelayQuad {}); + pd.cell_arcs.emplace_back(CellArc::ENDPOINT, async_clk_key.key.clock, DelayQuad{}); } // Combinational delays through cell for (auto &other_port : ci->ports) { @@ -140,7 +142,7 @@ void TimingAnalyser::get_cell_delays() } // Asynchronous startpoint else if (cls == TMG_STARTPOINT) { - pd.cell_arcs.emplace_back(CellArc::STARTPOINT, async_clk_key.key.clock, DelayQuad {}); + pd.cell_arcs.emplace_back(CellArc::STARTPOINT, async_clk_key.key.clock, DelayQuad{}); } // Combinational delays through cell for (auto &other_port : ci->ports) { @@ -1257,7 +1259,6 @@ struct Timing } }; - CriticalPath build_critical_path_report(Context *ctx, ClockPair &clocks, const PortRefVector &crit_path) { @@ -1514,8 +1515,8 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p auto sink_loc = ctx->getBelLocation(sink->bel); log_info("%4.1f %4.1f Net %s (%d,%d) -> (%d,%d)\n", ctx->getDelayNS(segment.delay), - ctx->getDelayNS(total), segment.net.c_str(ctx), - driver_loc.x, driver_loc.y, sink_loc.x, sink_loc.y); + ctx->getDelayNS(total), segment.net.c_str(ctx), driver_loc.x, driver_loc.y, sink_loc.x, + sink_loc.y); log_info(" Sink %s.%s\n", segment.to.first.c_str(ctx), segment.to.second.c_str(ctx)); const NetInfo *net = ctx->nets.at(segment.net).get(); @@ -1772,7 +1773,6 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p results.detailed_net_timings = std::move(detailed_net_timings); } - } NEXTPNR_NAMESPACE_END diff --git a/common/place/placer1.cc b/common/place/placer1.cc index df52471b..4ecf3a77 100644 --- a/common/place/placer1.cc +++ b/common/place/placer1.cc @@ -861,7 +861,7 @@ class SAPlacer return 0; if (ctx->getPortTimingClass(net->driver.cell, net->driver.port, cc) == TMG_IGNORE) return 0; - + float crit = tmg.get_criticality(CellPortKey(user)); double delay = ctx->getDelayNS(ctx->predictArcDelay(net, user)); return delay * std::pow(crit, crit_exp); diff --git a/common/route/router2.cc b/common/route/router2.cc index 17eef700..a54c58c9 100644 --- a/common/route/router2.cc +++ b/common/route/router2.cc @@ -583,8 +583,14 @@ struct Router2 wd.cost_bwd = cost; } - bool was_visited_fwd(int wire, float cost) { return flat_wires.at(wire).visited_fwd && flat_wires.at(wire).cost_fwd <= cost; } - bool was_visited_bwd(int wire, float cost) { return flat_wires.at(wire).visited_bwd && flat_wires.at(wire).cost_bwd <= cost; } + bool was_visited_fwd(int wire, float cost) + { + return flat_wires.at(wire).visited_fwd && flat_wires.at(wire).cost_fwd <= cost; + } + bool was_visited_bwd(int wire, float cost) + { + return flat_wires.at(wire).visited_bwd && flat_wires.at(wire).cost_bwd <= cost; + } float get_arc_crit(NetInfo *net, store_index i) { diff --git a/gowin/pack.cc b/gowin/pack.cc index 5e481196..00b5fee2 100644 --- a/gowin/pack.cc +++ b/gowin/pack.cc @@ -641,7 +641,7 @@ static void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constne auto it_param = uc->params.find(id_INIT); if (it_param == uc->params.end()) log_error("No initialization for lut found.\n"); - + int64_t uc_init = it_param->second.intval; int64_t mask = 0; uint8_t amt = 0; @@ -665,16 +665,17 @@ static void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constne if ((constnet->name == ctx->id("$PACKER_GND_NET"))) { uc_init = (uc_init & mask) | ((uc_init & mask) << amt); } else { - uc_init = (uc_init & (mask<> amt); + uc_init = (uc_init & (mask << amt)) | ((uc_init & (mask << amt)) >> amt); } size_t uc_init_len = it_param->second.to_string().length(); uc_init &= (1LL << uc_init_len) - 1; if (ctx->verbose) - log_info("%s lut config modified from 0x%lX to 0x%lX\n", ctx->nameOf(uc), it_param->second.intval, uc_init); + log_info("%s lut config modified from 0x%lX to 0x%lX\n", ctx->nameOf(uc), it_param->second.intval, + uc_init); - it_param->second = Property(uc_init, uc_init_len); + it_param->second = Property(uc_init, uc_init_len); uc->ports[user.port].net = nullptr; uc->ports[user.port].user_idx = {}; } else { diff --git a/mistral/delay.cc b/mistral/delay.cc index 19fa2237..1ef9be6b 100644 --- a/mistral/delay.cc +++ b/mistral/delay.cc @@ -368,8 +368,7 @@ bool Arch::getArcDelayOverride(const NetInfo *net_info, const PortRef &sink, Del cyclonev->rnode_timing_build_input_wave(src.node, temp, CycloneV::DELAY_MAX, inverted ? mistral::CycloneV::RF_RISE : mistral::CycloneV::RF_FALL, est, input_wave[1]); - if (input_wave[mistral::CycloneV::RF_RISE].empty() || - input_wave[mistral::CycloneV::RF_FALL].empty()) + if (input_wave[mistral::CycloneV::RF_RISE].empty() || input_wave[mistral::CycloneV::RF_FALL].empty()) return false; } diff --git a/mistral/pack.cc b/mistral/pack.cc index c0a71e33..a298c5d6 100644 --- a/mistral/pack.cc +++ b/mistral/pack.cc @@ -395,7 +395,8 @@ struct MistralPacker NPNR_ASSERT(dbits == 1 || dbits == 2 || dbits == 5 || dbits == 10 || dbits == 20 || dbits == 40); NPNR_ASSERT((1 << abits) * dbits <= 10240); - log_info("Setting up %ld-bit address, %ld-bit data M10K for %s.\n", abits, dbits, ci->name.str(ctx).c_str()); + log_info("Setting up %ld-bit address, %ld-bit data M10K for %s.\n", abits, dbits, + ci->name.str(ctx).c_str()); // Quartus doesn't seem to generate ADDRSTALL[AB], BYTEENABLE[AB][01]. @@ -425,8 +426,10 @@ struct MistralPacker ci->pin_data[ctx->id("B1ADDR[0]")].bel_pins = {ctx->id("DATABIN[19]")}; } for (int bit = bit_offset; bit < abits; bit++) { - ci->pin_data[ctx->idf("A1ADDR[%d]", bit)].bel_pins = {ctx->idf("ADDRA[%d]", bit + addr_offset - bit_offset)}; - ci->pin_data[ctx->idf("B1ADDR[%d]", bit)].bel_pins = {ctx->idf("ADDRB[%d]", bit + addr_offset - bit_offset)}; + ci->pin_data[ctx->idf("A1ADDR[%d]", bit)].bel_pins = { + ctx->idf("ADDRA[%d]", bit + addr_offset - bit_offset)}; + ci->pin_data[ctx->idf("B1ADDR[%d]", bit)].bel_pins = { + ctx->idf("ADDRB[%d]", bit + addr_offset - bit_offset)}; } // Data lines @@ -475,7 +478,8 @@ struct MistralPacker if (dbits == 40) for (int bit = bit_offset; bit < dbits; bit++) - ci->pin_data[ctx->idf("A1DATA[%d]", bit)].bel_pins.push_back(ctx->idf("DATABIN[%d]", bit - bit_offset)); + ci->pin_data[ctx->idf("A1DATA[%d]", bit)].bel_pins.push_back( + ctx->idf("DATABIN[%d]", bit - bit_offset)); // Read port if (dbits == 40)