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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2023-06-20 10:58:18 +02:00
parent 914999673c
commit 54b2045726
6 changed files with 31 additions and 21 deletions
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16
common/kernel/timing.cc
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@ -30,7 +30,8 @@
NEXTPNR_NAMESPACE_BEGIN NEXTPNR_NAMESPACE_BEGIN
namespace { namespace {
std::string clock_event_name(const Context *ctx, ClockDomainKey &dom) { std::string clock_event_name(const Context *ctx, ClockDomainKey &dom)
{
std::string value; std::string value;
if (dom.is_async()) if (dom.is_async())
value = "<async>"; value = "<async>";
@ -41,7 +42,8 @@ std::string clock_event_name(const Context *ctx, ClockDomainKey &dom) {
} }
} // namespace } // namespace
TimingAnalyser::TimingAnalyser(Context *ctx) : ctx(ctx) { TimingAnalyser::TimingAnalyser(Context *ctx) : ctx(ctx)
{
ClockDomainKey key{IdString(), ClockEdge::RISING_EDGE}; ClockDomainKey key{IdString(), ClockEdge::RISING_EDGE};
domain_to_id.emplace(key, 0); domain_to_id.emplace(key, 0);
domains.emplace_back(key); domains.emplace_back(key);
@ -115,7 +117,7 @@ void TimingAnalyser::get_cell_delays()
} }
// asynchronous endpoint // asynchronous endpoint
else if (cls == TMG_ENDPOINT) { else if (cls == TMG_ENDPOINT) {
pd.cell_arcs.emplace_back(CellArc::ENDPOINT, async_clk_key.key.clock, DelayQuad {}); pd.cell_arcs.emplace_back(CellArc::ENDPOINT, async_clk_key.key.clock, DelayQuad{});
} }
// Combinational delays through cell // Combinational delays through cell
for (auto &other_port : ci->ports) { for (auto &other_port : ci->ports) {
@ -140,7 +142,7 @@ void TimingAnalyser::get_cell_delays()
} }
// Asynchronous startpoint // Asynchronous startpoint
else if (cls == TMG_STARTPOINT) { else if (cls == TMG_STARTPOINT) {
pd.cell_arcs.emplace_back(CellArc::STARTPOINT, async_clk_key.key.clock, DelayQuad {}); pd.cell_arcs.emplace_back(CellArc::STARTPOINT, async_clk_key.key.clock, DelayQuad{});
} }
// Combinational delays through cell // Combinational delays through cell
for (auto &other_port : ci->ports) { for (auto &other_port : ci->ports) {
@ -1257,7 +1259,6 @@ struct Timing
} }
}; };
CriticalPath build_critical_path_report(Context *ctx, ClockPair &clocks, const PortRefVector &crit_path) CriticalPath build_critical_path_report(Context *ctx, ClockPair &clocks, const PortRefVector &crit_path)
{ {
@ -1514,8 +1515,8 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
auto sink_loc = ctx->getBelLocation(sink->bel); auto sink_loc = ctx->getBelLocation(sink->bel);
log_info("%4.1f %4.1f Net %s (%d,%d) -> (%d,%d)\n", ctx->getDelayNS(segment.delay), log_info("%4.1f %4.1f Net %s (%d,%d) -> (%d,%d)\n", ctx->getDelayNS(segment.delay),
ctx->getDelayNS(total), segment.net.c_str(ctx), ctx->getDelayNS(total), segment.net.c_str(ctx), driver_loc.x, driver_loc.y, sink_loc.x,
driver_loc.x, driver_loc.y, sink_loc.x, sink_loc.y); sink_loc.y);
log_info(" Sink %s.%s\n", segment.to.first.c_str(ctx), segment.to.second.c_str(ctx)); log_info(" Sink %s.%s\n", segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
const NetInfo *net = ctx->nets.at(segment.net).get(); const NetInfo *net = ctx->nets.at(segment.net).get();
@ -1772,7 +1773,6 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
results.detailed_net_timings = std::move(detailed_net_timings); results.detailed_net_timings = std::move(detailed_net_timings);
} }
} }
NEXTPNR_NAMESPACE_END NEXTPNR_NAMESPACE_END

2
common/place/placer1.cc
View File

@ -861,7 +861,7 @@ class SAPlacer
return 0; return 0;
if (ctx->getPortTimingClass(net->driver.cell, net->driver.port, cc) == TMG_IGNORE) if (ctx->getPortTimingClass(net->driver.cell, net->driver.port, cc) == TMG_IGNORE)
return 0; return 0;
float crit = tmg.get_criticality(CellPortKey(user)); float crit = tmg.get_criticality(CellPortKey(user));
double delay = ctx->getDelayNS(ctx->predictArcDelay(net, user)); double delay = ctx->getDelayNS(ctx->predictArcDelay(net, user));
return delay * std::pow(crit, crit_exp); return delay * std::pow(crit, crit_exp);

10
common/route/router2.cc
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@ -583,8 +583,14 @@ struct Router2
wd.cost_bwd = cost; wd.cost_bwd = cost;
} }
bool was_visited_fwd(int wire, float cost) { return flat_wires.at(wire).visited_fwd && flat_wires.at(wire).cost_fwd <= cost; } bool was_visited_fwd(int wire, float cost)
bool was_visited_bwd(int wire, float cost) { return flat_wires.at(wire).visited_bwd && flat_wires.at(wire).cost_bwd <= cost; } {
return flat_wires.at(wire).visited_fwd && flat_wires.at(wire).cost_fwd <= cost;
}
bool was_visited_bwd(int wire, float cost)
{
return flat_wires.at(wire).visited_bwd && flat_wires.at(wire).cost_bwd <= cost;
}
float get_arc_crit(NetInfo *net, store_index<PortRef> i) float get_arc_crit(NetInfo *net, store_index<PortRef> i)
{ {

9
gowin/pack.cc
View File

@ -641,7 +641,7 @@ static void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constne
auto it_param = uc->params.find(id_INIT); auto it_param = uc->params.find(id_INIT);
if (it_param == uc->params.end()) if (it_param == uc->params.end())
log_error("No initialization for lut found.\n"); log_error("No initialization for lut found.\n");
int64_t uc_init = it_param->second.intval; int64_t uc_init = it_param->second.intval;
int64_t mask = 0; int64_t mask = 0;
uint8_t amt = 0; uint8_t amt = 0;
@ -665,16 +665,17 @@ static void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constne
if ((constnet->name == ctx->id("$PACKER_GND_NET"))) { if ((constnet->name == ctx->id("$PACKER_GND_NET"))) {
uc_init = (uc_init & mask) | ((uc_init & mask) << amt); uc_init = (uc_init & mask) | ((uc_init & mask) << amt);
} else { } else {
uc_init = (uc_init & (mask<<amt)) | ((uc_init & (mask<<amt)) >> amt); uc_init = (uc_init & (mask << amt)) | ((uc_init & (mask << amt)) >> amt);
} }
size_t uc_init_len = it_param->second.to_string().length(); size_t uc_init_len = it_param->second.to_string().length();
uc_init &= (1LL << uc_init_len) - 1; uc_init &= (1LL << uc_init_len) - 1;
if (ctx->verbose) if (ctx->verbose)
log_info("%s lut config modified from 0x%lX to 0x%lX\n", ctx->nameOf(uc), it_param->second.intval, uc_init); log_info("%s lut config modified from 0x%lX to 0x%lX\n", ctx->nameOf(uc), it_param->second.intval,
uc_init);
it_param->second = Property(uc_init, uc_init_len); it_param->second = Property(uc_init, uc_init_len);
uc->ports[user.port].net = nullptr; uc->ports[user.port].net = nullptr;
uc->ports[user.port].user_idx = {}; uc->ports[user.port].user_idx = {};
} else { } else {

3
mistral/delay.cc
View File

@ -368,8 +368,7 @@ bool Arch::getArcDelayOverride(const NetInfo *net_info, const PortRef &sink, Del
cyclonev->rnode_timing_build_input_wave(src.node, temp, CycloneV::DELAY_MAX, cyclonev->rnode_timing_build_input_wave(src.node, temp, CycloneV::DELAY_MAX,
inverted ? mistral::CycloneV::RF_RISE : mistral::CycloneV::RF_FALL, inverted ? mistral::CycloneV::RF_RISE : mistral::CycloneV::RF_FALL,
est, input_wave[1]); est, input_wave[1]);
if (input_wave[mistral::CycloneV::RF_RISE].empty() || if (input_wave[mistral::CycloneV::RF_RISE].empty() || input_wave[mistral::CycloneV::RF_FALL].empty())
input_wave[mistral::CycloneV::RF_FALL].empty())
return false; return false;
} }

12
mistral/pack.cc
View File

@ -395,7 +395,8 @@ struct MistralPacker
NPNR_ASSERT(dbits == 1 || dbits == 2 || dbits == 5 || dbits == 10 || dbits == 20 || dbits == 40); NPNR_ASSERT(dbits == 1 || dbits == 2 || dbits == 5 || dbits == 10 || dbits == 20 || dbits == 40);
NPNR_ASSERT((1 << abits) * dbits <= 10240); NPNR_ASSERT((1 << abits) * dbits <= 10240);
log_info("Setting up %ld-bit address, %ld-bit data M10K for %s.\n", abits, dbits, ci->name.str(ctx).c_str()); log_info("Setting up %ld-bit address, %ld-bit data M10K for %s.\n", abits, dbits,
ci->name.str(ctx).c_str());
// Quartus doesn't seem to generate ADDRSTALL[AB], BYTEENABLE[AB][01]. // Quartus doesn't seem to generate ADDRSTALL[AB], BYTEENABLE[AB][01].
@ -425,8 +426,10 @@ struct MistralPacker
ci->pin_data[ctx->id("B1ADDR[0]")].bel_pins = {ctx->id("DATABIN[19]")}; ci->pin_data[ctx->id("B1ADDR[0]")].bel_pins = {ctx->id("DATABIN[19]")};
} }
for (int bit = bit_offset; bit < abits; bit++) { for (int bit = bit_offset; bit < abits; bit++) {
ci->pin_data[ctx->idf("A1ADDR[%d]", bit)].bel_pins = {ctx->idf("ADDRA[%d]", bit + addr_offset - bit_offset)}; ci->pin_data[ctx->idf("A1ADDR[%d]", bit)].bel_pins = {
ci->pin_data[ctx->idf("B1ADDR[%d]", bit)].bel_pins = {ctx->idf("ADDRB[%d]", bit + addr_offset - bit_offset)}; ctx->idf("ADDRA[%d]", bit + addr_offset - bit_offset)};
ci->pin_data[ctx->idf("B1ADDR[%d]", bit)].bel_pins = {
ctx->idf("ADDRB[%d]", bit + addr_offset - bit_offset)};
} }
// Data lines // Data lines
@ -475,7 +478,8 @@ struct MistralPacker
if (dbits == 40) if (dbits == 40)
for (int bit = bit_offset; bit < dbits; bit++) for (int bit = bit_offset; bit < dbits; bit++)
ci->pin_data[ctx->idf("A1DATA[%d]", bit)].bel_pins.push_back(ctx->idf("DATABIN[%d]", bit - bit_offset)); ci->pin_data[ctx->idf("A1DATA[%d]", bit)].bel_pins.push_back(
ctx->idf("DATABIN[%d]", bit - bit_offset));
// Read port // Read port
if (dbits == 40) if (dbits == 40)