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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2023-06-20 10:58:18 +02:00
parent 914999673c
commit 54b2045726
6 changed files with 31 additions and 21 deletions
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12
common/kernel/timing.cc
View File

@ -30,7 +30,8 @@
NEXTPNR_NAMESPACE_BEGIN
namespace {
std::string clock_event_name(const Context *ctx, ClockDomainKey &dom) {
std::string clock_event_name(const Context *ctx, ClockDomainKey &dom)
{
std::string value;
if (dom.is_async())
value = "<async>";
@ -41,7 +42,8 @@ std::string clock_event_name(const Context *ctx, ClockDomainKey &dom) {
}
} // namespace
TimingAnalyser::TimingAnalyser(Context *ctx) : ctx(ctx) {
TimingAnalyser::TimingAnalyser(Context *ctx) : ctx(ctx)
{
ClockDomainKey key{IdString(), ClockEdge::RISING_EDGE};
domain_to_id.emplace(key, 0);
domains.emplace_back(key);
@ -1257,7 +1259,6 @@ struct Timing
}
};
CriticalPath build_critical_path_report(Context *ctx, ClockPair &clocks, const PortRefVector &crit_path)
{
@ -1514,8 +1515,8 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
auto sink_loc = ctx->getBelLocation(sink->bel);
log_info("%4.1f %4.1f Net %s (%d,%d) -> (%d,%d)\n", ctx->getDelayNS(segment.delay),
ctx->getDelayNS(total), segment.net.c_str(ctx),
driver_loc.x, driver_loc.y, sink_loc.x, sink_loc.y);
ctx->getDelayNS(total), segment.net.c_str(ctx), driver_loc.x, driver_loc.y, sink_loc.x,
sink_loc.y);
log_info(" Sink %s.%s\n", segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
const NetInfo *net = ctx->nets.at(segment.net).get();
@ -1772,7 +1773,6 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
results.detailed_net_timings = std::move(detailed_net_timings);
}
}
NEXTPNR_NAMESPACE_END

10
common/route/router2.cc
View File

@ -583,8 +583,14 @@ struct Router2
wd.cost_bwd = cost;
}
bool was_visited_fwd(int wire, float cost) { return flat_wires.at(wire).visited_fwd && flat_wires.at(wire).cost_fwd <= cost; }
bool was_visited_bwd(int wire, float cost) { return flat_wires.at(wire).visited_bwd && flat_wires.at(wire).cost_bwd <= cost; }
bool was_visited_fwd(int wire, float cost)
{
return flat_wires.at(wire).visited_fwd && flat_wires.at(wire).cost_fwd <= cost;
}
bool was_visited_bwd(int wire, float cost)
{
return flat_wires.at(wire).visited_bwd && flat_wires.at(wire).cost_bwd <= cost;
}
float get_arc_crit(NetInfo *net, store_index<PortRef> i)
{

3
gowin/pack.cc
View File

@ -672,7 +672,8 @@ static void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constne
uc_init &= (1LL << uc_init_len) - 1;
if (ctx->verbose)
log_info("%s lut config modified from 0x%lX to 0x%lX\n", ctx->nameOf(uc), it_param->second.intval, uc_init);
log_info("%s lut config modified from 0x%lX to 0x%lX\n", ctx->nameOf(uc), it_param->second.intval,
uc_init);
it_param->second = Property(uc_init, uc_init_len);
uc->ports[user.port].net = nullptr;

3
mistral/delay.cc
View File

@ -368,8 +368,7 @@ bool Arch::getArcDelayOverride(const NetInfo *net_info, const PortRef &sink, Del
cyclonev->rnode_timing_build_input_wave(src.node, temp, CycloneV::DELAY_MAX,
inverted ? mistral::CycloneV::RF_RISE : mistral::CycloneV::RF_FALL,
est, input_wave[1]);
if (input_wave[mistral::CycloneV::RF_RISE].empty() ||
input_wave[mistral::CycloneV::RF_FALL].empty())
if (input_wave[mistral::CycloneV::RF_RISE].empty() || input_wave[mistral::CycloneV::RF_FALL].empty())
return false;
}

12
mistral/pack.cc
View File

@ -395,7 +395,8 @@ struct MistralPacker
NPNR_ASSERT(dbits == 1 || dbits == 2 || dbits == 5 || dbits == 10 || dbits == 20 || dbits == 40);
NPNR_ASSERT((1 << abits) * dbits <= 10240);
log_info("Setting up %ld-bit address, %ld-bit data M10K for %s.\n", abits, dbits, ci->name.str(ctx).c_str());
log_info("Setting up %ld-bit address, %ld-bit data M10K for %s.\n", abits, dbits,
ci->name.str(ctx).c_str());
// Quartus doesn't seem to generate ADDRSTALL[AB], BYTEENABLE[AB][01].
@ -425,8 +426,10 @@ struct MistralPacker
ci->pin_data[ctx->id("B1ADDR[0]")].bel_pins = {ctx->id("DATABIN[19]")};
}
for (int bit = bit_offset; bit < abits; bit++) {
ci->pin_data[ctx->idf("A1ADDR[%d]", bit)].bel_pins = {ctx->idf("ADDRA[%d]", bit + addr_offset - bit_offset)};
ci->pin_data[ctx->idf("B1ADDR[%d]", bit)].bel_pins = {ctx->idf("ADDRB[%d]", bit + addr_offset - bit_offset)};
ci->pin_data[ctx->idf("A1ADDR[%d]", bit)].bel_pins = {
ctx->idf("ADDRA[%d]", bit + addr_offset - bit_offset)};
ci->pin_data[ctx->idf("B1ADDR[%d]", bit)].bel_pins = {
ctx->idf("ADDRB[%d]", bit + addr_offset - bit_offset)};
}
// Data lines
@ -475,7 +478,8 @@ struct MistralPacker
if (dbits == 40)
for (int bit = bit_offset; bit < dbits; bit++)
ci->pin_data[ctx->idf("A1DATA[%d]", bit)].bel_pins.push_back(ctx->idf("DATABIN[%d]", bit - bit_offset));
ci->pin_data[ctx->idf("A1DATA[%d]", bit)].bel_pins.push_back(
ctx->idf("DATABIN[%d]", bit - bit_offset));
// Read port
if (dbits == 40)