Merge pull request #382 from YosysHQ/ecp5-psuedodiff
ecp5: Add support for top pseudo diff outputs
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commit
54c1bc1538
@ -256,6 +256,18 @@ static std::string get_pic_tile(Context *ctx, BelId bel)
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}
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}
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// Get the complement PIC and PIO tiles for a pseudo differential IO
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static std::string get_comp_pio_tile(Context *ctx, BelId bel)
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{
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NPNR_ASSERT(bel.location.y == 0);
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return ctx->getTileByTypeAndLocation(0, bel.location.x + 1, "PIOT1");
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}
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static std::string get_comp_pic_tile(Context *ctx, BelId bel)
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{
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NPNR_ASSERT(bel.location.y == 0);
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return ctx->getTileByTypeAndLocation(1, bel.location.x + 1, "PICT1");
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}
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// Get the list of tiles corresponding to a blockram
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std::vector<std::string> get_bram_tiles(Context *ctx, BelId bel)
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{
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@ -829,18 +841,29 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
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cc.tiles[pio_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
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cc.tiles[pic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
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if (is_differential(ioType_from_str(iotype))) {
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// Explicitly disable other pair
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std::string other;
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if (pio == "PIOA")
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other = "PIOB";
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else if (pio == "PIOC")
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other = "PIOD";
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else
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log_error("cannot place differential IO at location %s\n", pio.c_str());
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// cc.tiles[pio_tile].add_enum(other + ".BASE_TYPE", "_NONE_");
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// cc.tiles[pic_tile].add_enum(other + ".BASE_TYPE", "_NONE_");
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cc.tiles[pio_tile].add_enum(other + ".PULLMODE", "NONE");
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cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE");
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if (bel.location.y == 0) {
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// Pseudo differential top IO
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NPNR_ASSERT(dir == "OUTPUT");
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NPNR_ASSERT(pio == "PIOA");
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std::string cpio_tile = get_comp_pio_tile(ctx, bel);
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std::string cpic_tile = get_comp_pic_tile(ctx, bel);
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cc.tiles[cpio_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
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cc.tiles[cpic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
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} else {
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// Explicitly disable other pair
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std::string other;
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if (pio == "PIOA")
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other = "PIOB";
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else if (pio == "PIOC")
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other = "PIOD";
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else
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log_error("cannot place differential IO at location %s\n", pio.c_str());
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// cc.tiles[pio_tile].add_enum(other + ".BASE_TYPE", "_NONE_");
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// cc.tiles[pic_tile].add_enum(other + ".BASE_TYPE", "_NONE_");
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cc.tiles[pio_tile].add_enum(other + ".PULLMODE", "NONE");
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cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE");
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}
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} else if (is_referenced(ioType_from_str(iotype))) {
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cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE");
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}
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@ -22,6 +22,8 @@ X(SSTL15D_II)
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X(HSUL12D)
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X(LVCMOS33D)
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X(LVCMOS25D)
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X(LVCMOS15D)
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X(LVCMOS12D)
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X(LVDS)
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X(BLVDS25)
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@ -109,6 +109,7 @@ IOVoltage get_vccio(IOType type)
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case IOType::SSTL18D_II:
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return IOVoltage::VCC_1V8;
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case IOType::LVCMOS15:
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case IOType::LVCMOS15D:
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case IOType::SSTL15_I:
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case IOType::SSTL15_II:
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case IOType::SSTL15D_I:
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@ -120,6 +121,7 @@ IOVoltage get_vccio(IOType type)
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case IOType::SSTL135D_II:
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return IOVoltage::VCC_1V35;
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case IOType::LVCMOS12:
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case IOType::LVCMOS12D:
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case IOType::HSUL12:
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case IOType::HSUL12D:
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return IOVoltage::VCC_1V2;
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@ -159,6 +161,8 @@ bool is_differential(IOType type)
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switch (type) {
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case IOType::LVCMOS33D:
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case IOType::LVCMOS25D:
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case IOType::LVCMOS15D:
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case IOType::LVCMOS12D:
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case IOType::LVPECL33:
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case IOType::LVDS:
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case IOType::MLVDS25:
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@ -207,7 +211,7 @@ bool valid_loc_for_io(IOType type, PortType dir, IOSide side, int z)
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bool is_lr = side == IOSide::LEFT || side == IOSide::RIGHT;
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if (is_referenced(type) && !is_lr)
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return false;
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if (is_differential(type) && (!is_lr || ((z % 2) == 1)))
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if (is_differential(type) && ((!is_lr && dir != PORT_OUT) || ((z % 2) == 1)))
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return false;
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if ((type == IOType::LVCMOS18D || type == IOType::LVDS) && (dir == PORT_OUT || dir == PORT_INOUT) && z != 0)
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return false;
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