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Add ice40 wire attributes (grid position, segment list)

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-08-18 14:14:27 +02:00
parent 74eebc489f
commit 5500cf3aff
3 changed files with 45 additions and 18 deletions
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33
ice40/arch.cc
View File

@ -226,6 +226,12 @@ PortType Arch::getBelPinType(BelId bel, IdString pin) const
return PORT_INOUT;
}
std::vector<std::pair<IdString, std::string>> Arch::getBelAttrs(BelId) const
{
std::vector<std::pair<IdString, std::string>> ret;
return ret;
}
WireId Arch::getBelPinWire(BelId bel, IdString pin) const
{
WireId ret;
@ -331,6 +337,24 @@ IdString Arch::getWireType(WireId wire) const
return IdString();
}
std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) const
{
std::vector<std::pair<IdString, std::string>> ret;
auto &wi = chip_info->wire_data[wire.index];
ret.push_back(std::make_pair(id("GRID_X"), stringf("%d", wi.x)));
ret.push_back(std::make_pair(id("GRID_Y"), stringf("%d", wi.y)));
ret.push_back(std::make_pair(id("GRID_Z"), stringf("%d", wi.z)));
for (int i = 0; i < wi.num_segments; i++) {
auto &si = wi.segments[i];
ret.push_back(std::make_pair(id(stringf("segment[%d]", i)),
stringf("X%d/Y%d/%s", si.x, si.y, chip_info->tile_wire_names[si.index].get())));
}
return ret;
}
// -----------------------------------------------------------------------
PipId Arch::getPipByName(IdString name) const
@ -372,6 +396,15 @@ IdString Arch::getPipName(PipId pip) const
#endif
}
IdString Arch::getPipType(PipId pip) const { return IdString(); }
std::vector<std::pair<IdString, std::string>> Arch::getPipAttrs(PipId) const
{
std::vector<std::pair<IdString, std::string>> ret;
return ret;
}
// -----------------------------------------------------------------------
BelId Arch::getPackagePinBel(const std::string &pin) const

23
ice40/arch.h
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@ -225,6 +225,7 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD {
RelPtr<BelConfigPOD> bel_config;
RelPtr<PackageInfoPOD> packages_data;
RelPtr<CellTimingPOD> cell_timing;
RelPtr<RelPtr<char>> tile_wire_names;
});
#if defined(_MSC_VER)
@ -502,11 +503,7 @@ struct Arch : BaseCtx
return IdString(chip_info->bel_data[bel.index].type);
}
std::vector<std::pair<IdString, std::string>> getBelAttrs(BelId) const
{
std::vector<std::pair<IdString, std::string>> ret;
return ret;
}
std::vector<std::pair<IdString, std::string>> getBelAttrs(BelId bel) const;
WireId getBelPinWire(BelId bel, IdString pin) const;
PortType getBelPinType(BelId bel, IdString pin) const;
@ -523,12 +520,7 @@ struct Arch : BaseCtx
}
IdString getWireType(WireId wire) const;
std::vector<std::pair<IdString, std::string>> getWireAttrs(WireId) const
{
std::vector<std::pair<IdString, std::string>> ret;
return ret;
}
std::vector<std::pair<IdString, std::string>> getWireAttrs(WireId wire) const;
uint32_t getWireChecksum(WireId wire) const { return wire.index; }
@ -704,13 +696,8 @@ struct Arch : BaseCtx
IdString getPipName(PipId pip) const;
IdString getPipType(PipId pip) const { return IdString(); }
std::vector<std::pair<IdString, std::string>> getPipAttrs(PipId) const
{
std::vector<std::pair<IdString, std::string>> ret;
return ret;
}
IdString getPipType(PipId pip) const;
std::vector<std::pair<IdString, std::string>> getPipAttrs(PipId pip) const;
uint32_t getPipChecksum(PipId pip) const { return pip.index; }

7
ice40/chipdb.py
View File

@ -50,6 +50,7 @@ tiletypes = dict()
wiretypes = dict()
gfx_wire_ids = dict()
gfx_wire_names = list()
wire_segments = dict()
fast_timings = None
@ -93,6 +94,7 @@ with open(args.gfxh) as f:
idx = len(gfx_wire_ids)
name = line.strip().rstrip(",")
gfx_wire_ids[name] = idx
gfx_wire_names.append(name)
def read_timings(filename):
db = dict()
@ -932,6 +934,10 @@ bba.post('NEXTPNR_NAMESPACE_END')
bba.push("chipdb_blob_%s" % dev_name)
bba.r("chip_info_%s" % dev_name, "chip_info")
bba.l("tile_wire_names")
for name in gfx_wire_names:
bba.s(name, name)
for bel in range(len(bel_name)):
bba.l("bel_wires_%d" % bel, "BelWirePOD")
for data in sorted(bel_wires[bel]):
@ -1276,5 +1282,6 @@ bba.r("bits_info_%s" % dev_name, "bits_info")
bba.r("bel_config_%s" % dev_name if len(extra_cell_config) > 0 else None, "bel_config")
bba.r("package_info_%s" % dev_name, "packages_data")
bba.r("cell_timings_%s" % dev_name, "cell_timing")
bba.r("tile_wire_names", "tile_wire_names")
bba.pop()