Initial FPGA interchange (which is just a cut-down xilinx arch).
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman
parent
c99fbde0eb
commit
561b519716
@ -66,9 +66,9 @@ endif()
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set(PROGRAM_PREFIX "" CACHE STRING "Name prefix for executables")
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# List of families to build
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set(FAMILIES generic ice40 ecp5 nexus gowin)
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set(FAMILIES generic ice40 ecp5 nexus gowin fpga_interchange)
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set(STABLE_FAMILIES generic ice40 ecp5)
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set(EXPERIMENTAL_FAMILIES nexus gowin)
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set(EXPERIMENTAL_FAMILIES nexus gowin fpga_interchange)
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set(ARCH "" CACHE STRING "Architecture family for nextpnr build")
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set_property(CACHE ARCH PROPERTY STRINGS ${FAMILIES})
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474
fpga_interchange/arch.cc
Normal file
474
fpga_interchange/arch.cc
Normal file
@ -0,0 +1,474 @@
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/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
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* Copyright (C) 2018-19 David Shah <david@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include <algorithm>
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#include <boost/algorithm/string.hpp>
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#include <boost/range/adaptor/reversed.hpp>
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#include <cmath>
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#include <cstring>
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#include <queue>
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#include "log.h"
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#include "nextpnr.h"
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#include "placer1.h"
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#include "placer_heap.h"
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#include "router1.h"
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#include "router2.h"
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#include "timing.h"
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#include "util.h"
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NEXTPNR_NAMESPACE_BEGIN
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static std::pair<std::string, std::string> split_identifier_name(const std::string &name)
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{
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size_t first_slash = name.find('/');
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NPNR_ASSERT(first_slash != std::string::npos);
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return std::make_pair(name.substr(0, first_slash), name.substr(first_slash + 1));
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};
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static std::pair<std::string, std::string> split_identifier_name_dot(const std::string &name)
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{
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size_t first_dot = name.find('.');
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NPNR_ASSERT(first_dot != std::string::npos);
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return std::make_pair(name.substr(0, first_dot), name.substr(first_dot + 1));
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};
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// -----------------------------------------------------------------------
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void IdString::initialize_arch(const BaseCtx *ctx)
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{
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#define X(t) initialize_add(ctx, #t, ID_##t);
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#include "constids.inc"
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#undef X
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}
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// -----------------------------------------------------------------------
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static const ChipInfoPOD *get_chip_info(const RelPtr<ChipInfoPOD> *ptr) { return ptr->get(); }
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Arch::Arch(ArchArgs args) : args(args)
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{
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try {
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blob_file.open(args.chipdb);
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if (args.chipdb.empty() || !blob_file.is_open())
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log_error("Unable to read chipdb %s\n", args.chipdb.c_str());
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const char *blob = reinterpret_cast<const char *>(blob_file.data());
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chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(blob));
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} catch (...) {
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log_error("Unable to read chipdb %s\n", args.chipdb.c_str());
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}
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tileStatus.resize(chip_info->num_tiles);
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for (int i = 0; i < chip_info->num_tiles; i++) {
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tileStatus[i].boundcells.resize(chip_info->tile_types[chip_info->tiles[i].type].num_bels);
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}
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}
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// -----------------------------------------------------------------------
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std::string Arch::getChipName() const { return chip_info->name.get(); }
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// -----------------------------------------------------------------------
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IdString Arch::archArgsToId(ArchArgs args) const { return IdString(); }
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// -----------------------------------------------------------------------
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void Arch::setup_byname() const
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{
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if (tile_by_name.empty()) {
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for (int i = 0; i < chip_info->num_tiles; i++) {
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tile_by_name[chip_info->tiles[i].name.get()] = i;
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}
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}
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if (site_by_name.empty()) {
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for (int i = 0; i < chip_info->num_tiles; i++) {
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auto &tile = chip_info->tiles[i];
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auto &tile_type = chip_info->tile_types[tile.type];
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for (int j = 0; j < tile_type.number_sites; j++) {
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auto &site = chip_info->sites[tile.sites[j]];
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site_by_name[site.name.get()] = std::make_pair(i, j);
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}
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}
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}
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}
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BelId Arch::getBelByName(IdString name) const
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{
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BelId ret;
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setup_byname();
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auto split = split_identifier_name(name.str(this));
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int tile, site;
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std::tie(tile, site) = site_by_name.at(split.first);
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auto &tile_info = chip_info->tile_types[chip_info->tiles[tile].type];
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IdString belname = id(split.second);
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for (int i = 0; i < tile_info.num_bels; i++) {
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if (tile_info.bel_data[i].site == site && tile_info.bel_data[i].name == belname.index) {
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ret.tile = tile;
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ret.index = i;
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break;
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}
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}
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return ret;
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}
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BelRange Arch::getBelsByTile(int x, int y) const
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{
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BelRange br;
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br.b.cursor_tile = getTileIndex(x, y);
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br.e.cursor_tile = br.b.cursor_tile;
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br.b.cursor_index = 0;
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br.e.cursor_index = chip_info->tile_types[chip_info->tiles[br.b.cursor_tile].type].num_bels;
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br.b.chip = chip_info;
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br.e.chip = chip_info;
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if (br.e.cursor_index == -1)
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++br.e.cursor_index;
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else
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++br.e;
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return br;
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}
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WireId Arch::getBelPinWire(BelId bel, IdString pin) const
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{
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NPNR_ASSERT(bel != BelId());
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int num_bel_wires = locInfo(bel).bel_data[bel.index].num_bel_wires;
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const int32_t *ports = locInfo(bel).bel_data[bel.index].ports.get();
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for (int i = 0; i < num_bel_wires; i++) {
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if (ports[i] == pin.index) {
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const int32_t *wires = locInfo(bel).bel_data[bel.index].wires.get();
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int32_t wire_index = wires[i];
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return canonicalWireId(chip_info, bel.tile, wire_index);
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}
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}
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// Port could not be found!
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return WireId();
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}
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PortType Arch::getBelPinType(BelId bel, IdString pin) const
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{
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NPNR_ASSERT(bel != BelId());
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int num_bel_wires = locInfo(bel).bel_data[bel.index].num_bel_wires;
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const int32_t *ports = locInfo(bel).bel_data[bel.index].ports.get();
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for (int i = 0; i < num_bel_wires; i++) {
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if (ports[i] == pin.index) {
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const int32_t *types = locInfo(bel).bel_data[bel.index].types.get();
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return PortType(types[i]);
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}
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}
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return PORT_INOUT;
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}
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// -----------------------------------------------------------------------
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WireId Arch::getWireByName(IdString name) const
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{
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if (wire_by_name_cache.count(name))
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return wire_by_name_cache.at(name);
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WireId ret;
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setup_byname();
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const std::string &s = name.str(this);
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auto sp = split_identifier_name(s.substr(8));
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auto iter = site_by_name.find(sp.first);
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if (iter != site_by_name.end()) {
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int tile;
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int site;
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std::tie(tile, site) = iter->second;
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auto &tile_info = chip_info->tile_types[chip_info->tiles[tile].type];
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IdString wirename = id(sp.second);
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for (int i = 0; i < tile_info.num_wires; i++) {
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if (tile_info.wire_data[i].site == site && tile_info.wire_data[i].name == wirename.index) {
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ret.tile = tile;
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ret.index = i;
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break;
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}
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}
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} else {
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auto sp = split_identifier_name(s);
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int tile = tile_by_name.at(sp.first);
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auto &tile_info = chip_info->tile_types[chip_info->tiles[tile].type];
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IdString wirename = id(sp.second);
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for (int i = 0; i < tile_info.num_wires; i++) {
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if (tile_info.wire_data[i].site == -1 && tile_info.wire_data[i].name == wirename.index) {
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ret.tile = tile;
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ret.index = i;
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break;
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}
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}
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}
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wire_by_name_cache[name] = ret;
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return ret;
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}
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IdString Arch::getWireType(WireId wire) const { return id(""); }
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std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) const
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{
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return {};
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}
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// -----------------------------------------------------------------------
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PipId Arch::getPipByName(IdString name) const
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{
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if (pip_by_name_cache.count(name))
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return pip_by_name_cache.at(name);
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PipId ret;
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setup_byname();
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const std::string &s = name.str(this);
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auto sp = split_identifier_name(s.substr(8));
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auto iter = site_by_name.find(sp.first);
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if (iter != site_by_name.end()) {
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int tile;
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int site;
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std::tie(tile, site) = iter->second;
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auto &tile_info = chip_info->tile_types[chip_info->tiles[tile].type];
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auto sp3 = split_identifier_name(sp.second);
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IdString belname = id(sp3.first);
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IdString pinname = id(sp3.second);
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for (int i = 0; i < tile_info.num_pips; i++) {
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if (tile_info.pip_data[i].site == site && tile_info.pip_data[i].bel == belname.index &&
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tile_info.pip_data[i].extra_data == pinname.index) {
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ret.tile = tile;
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ret.index = i;
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break;
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}
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}
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} else {
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int tile = tile_by_name.at(sp.first);
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auto &tile_info = chip_info->tile_types[chip_info->tiles[tile].type];
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auto spn = split_identifier_name_dot(sp.second);
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int fromwire = std::stoi(spn.first), towire = std::stoi(spn.second);
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for (int i = 0; i < tile_info.num_pips; i++) {
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if (tile_info.pip_data[i].src_index == fromwire &&
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tile_info.pip_data[i].dst_index == towire) {
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ret.tile = tile;
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ret.index = i;
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break;
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}
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}
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}
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pip_by_name_cache[name] = ret;
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return ret;
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}
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IdString Arch::getPipName(PipId pip) const
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{
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NPNR_ASSERT(pip != PipId());
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if (locInfo(pip).pip_data[pip.index].site != -1) {
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auto site_index = chip_info->tiles[pip.tile].sites[locInfo(pip).pip_data[pip.index].site];
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auto &site = chip_info->sites[site_index];
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return id(site.name.get() + std::string("/") + IdString(locInfo(pip).pip_data[pip.index].bel).str(this) + "/" +
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IdString(locInfo(pip).wire_data[locInfo(pip).pip_data[pip.index].src_index].name).str(this));
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} else {
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return id(std::string(chip_info->tiles[pip.tile].name.get()) + "/" +
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std::to_string(locInfo(pip).pip_data[pip.index].src_index) + "." +
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std::to_string(locInfo(pip).pip_data[pip.index].dst_index));
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}
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}
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IdString Arch::getPipType(PipId pip) const { return id("PIP"); }
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std::vector<std::pair<IdString, std::string>> Arch::getPipAttrs(PipId pip) const { return {}; }
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// -----------------------------------------------------------------------
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std::vector<IdString> Arch::getBelPins(BelId bel) const
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{
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std::vector<IdString> ret;
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NPNR_ASSERT(bel != BelId());
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// FIXME: The std::vector here can be replaced by a int32_t -> IdString
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// range wrapper.
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int num_bel_wires = locInfo(bel).bel_data[bel.index].num_bel_wires;
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const int32_t *ports = locInfo(bel).bel_data[bel.index].ports.get();
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for (int i = 0; i < num_bel_wires; i++) {
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ret.push_back(IdString(ports[i]));
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}
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return ret;
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}
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BelId Arch::getBelByLocation(Loc loc) const
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{
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BelId bi;
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if (loc.x >= chip_info->width || loc.y >= chip_info->height)
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return BelId();
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bi.tile = getTileIndex(loc);
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auto &li = locInfo(bi);
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if(loc.z >= li.num_bels) {
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return BelId();
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} else {
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bi.index = loc.z;
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return bi;
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}
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}
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std::vector<std::pair<IdString, std::string>> Arch::getBelAttrs(BelId bel) const { return {}; }
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// -----------------------------------------------------------------------
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delay_t Arch::estimateDelay(WireId src, WireId dst, bool debug) const
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{
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return 0;
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}
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ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
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{
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int dst_tile = dst.tile == -1 ? chip_info->nodes[dst.index].tile_wires[0].tile : dst.tile;
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int src_tile = src.tile == -1 ? chip_info->nodes[src.index].tile_wires[0].tile : src.tile;
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int x0, x1, y0, y1;
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x0 = src_tile % chip_info->width;
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x1 = x0;
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y0 = src_tile / chip_info->width;
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y1 = y0;
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auto expand = [&](int x, int y) {
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x0 = std::min(x0, x);
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x1 = std::max(x1, x);
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y0 = std::min(y0, y);
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y1 = std::max(y1, y);
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};
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expand(dst_tile % chip_info->width, dst_tile / chip_info->width);
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if (source_locs.count(src))
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expand(source_locs.at(src).x, source_locs.at(src).y);
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if (sink_locs.count(dst)) {
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expand(sink_locs.at(dst).x, sink_locs.at(dst).y);
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}
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return {x0, y0, x1, y1};
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}
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delay_t Arch::getBoundingBoxCost(WireId src, WireId dst, int distance) const
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{
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return 0;
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}
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delay_t Arch::getWireRipupDelayPenalty(WireId wire) const
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{
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return getRipupDelayPenalty();
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}
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delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
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{
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return 0;
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}
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||||
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bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; }
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// -----------------------------------------------------------------------
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bool Arch::pack()
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{
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return false;
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||||
}
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bool Arch::place()
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{
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return false;
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||||
}
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||||
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||||
bool Arch::route()
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||||
{
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return false;
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||||
}
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||||
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||||
// -----------------------------------------------------------------------
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||||
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||||
std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
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||||
{
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||||
return {};
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||||
}
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||||
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||||
DecalXY Arch::getBelDecal(BelId bel) const
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||||
{
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||||
DecalXY decalxy;
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||||
return decalxy;
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||||
}
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||||
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||||
DecalXY Arch::getWireDecal(WireId wire) const
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||||
{
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||||
DecalXY decalxy;
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||||
return decalxy;
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||||
}
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||||
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||||
DecalXY Arch::getPipDecal(PipId pip) const { return {}; };
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||||
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||||
DecalXY Arch::getGroupDecal(GroupId pip) const { return {}; };
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||||
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||||
// -----------------------------------------------------------------------
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||||
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||||
bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
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||||
{
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||||
return false;
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||||
}
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||||
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TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const
|
||||
{
|
||||
return TMG_IGNORE;
|
||||
}
|
||||
|
||||
TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port, int index) const
|
||||
{
|
||||
TimingClockingInfo info;
|
||||
return info;
|
||||
}
|
||||
|
||||
#ifdef WITH_HEAP
|
||||
const std::string Arch::defaultPlacer = "heap";
|
||||
#else
|
||||
const std::string Arch::defaultPlacer = "sa";
|
||||
#endif
|
||||
|
||||
const std::vector<std::string> Arch::availablePlacers = {"sa",
|
||||
#ifdef WITH_HEAP
|
||||
"heap"
|
||||
#endif
|
||||
};
|
||||
|
||||
const std::string Arch::defaultRouter = "router2";
|
||||
const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
1096
fpga_interchange/arch.h
Normal file
1096
fpga_interchange/arch.h
Normal file
File diff suppressed because it is too large
Load Diff
74
fpga_interchange/arch_pybindings.cc
Normal file
74
fpga_interchange/arch_pybindings.cc
Normal file
@ -0,0 +1,74 @@
|
||||
/*
|
||||
* nextpnr -- Next Generation Place and Route
|
||||
*
|
||||
* Copyright (C) 2020 David Shah <dave@ds0.me>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef NO_PYTHON
|
||||
|
||||
#include "arch_pybindings.h"
|
||||
#include "nextpnr.h"
|
||||
#include "pybindings.h"
|
||||
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
void arch_wrap_python(py::module &m)
|
||||
{
|
||||
using namespace PythonConversion;
|
||||
py::class_<ArchArgs>(m, "ArchArgs").def_readwrite("chipdb", &ArchArgs::chipdb);
|
||||
|
||||
py::class_<BelId>(m, "BelId").def_readwrite("index", &BelId::index);
|
||||
|
||||
py::class_<WireId>(m, "WireId").def_readwrite("index", &WireId::index);
|
||||
|
||||
py::class_<PipId>(m, "PipId").def_readwrite("index", &PipId::index);
|
||||
|
||||
auto arch_cls = py::class_<Arch, BaseCtx>(m, "Arch").def(py::init<ArchArgs>());
|
||||
auto ctx_cls = py::class_<Context, Arch>(m, "Context")
|
||||
.def("checksum", &Context::checksum)
|
||||
.def("pack", &Context::pack)
|
||||
.def("place", &Context::place)
|
||||
.def("route", &Context::route);
|
||||
|
||||
fn_wrapper_2a<Context, decltype(&Context::isValidBelForCell), &Context::isValidBelForCell, pass_through<bool>,
|
||||
addr_and_unwrap<CellInfo>, conv_from_str<BelId>>::def_wrap(ctx_cls, "isValidBelForCell");
|
||||
|
||||
typedef std::unordered_map<IdString, std::unique_ptr<CellInfo>> CellMap;
|
||||
typedef std::unordered_map<IdString, std::unique_ptr<NetInfo>> NetMap;
|
||||
typedef std::unordered_map<IdString, IdString> AliasMap;
|
||||
typedef std::unordered_map<IdString, HierarchicalCell> HierarchyMap;
|
||||
|
||||
auto belpin_cls = py::class_<ContextualWrapper<BelPin>>(m, "BelPin");
|
||||
readonly_wrapper<BelPin, decltype(&BelPin::bel), &BelPin::bel, conv_to_str<BelId>>::def_wrap(belpin_cls, "bel");
|
||||
readonly_wrapper<BelPin, decltype(&BelPin::pin), &BelPin::pin, conv_to_str<IdString>>::def_wrap(belpin_cls, "pin");
|
||||
|
||||
#include "arch_pybindings_shared.h"
|
||||
|
||||
WRAP_RANGE(m, Bel, conv_to_str<BelId>);
|
||||
WRAP_RANGE(m, Wire, conv_to_str<WireId>);
|
||||
WRAP_RANGE(m, AllPip, conv_to_str<PipId>);
|
||||
WRAP_RANGE(m, UphillPip, conv_to_str<PipId>);
|
||||
WRAP_RANGE(m, DownhillPip, conv_to_str<PipId>);
|
||||
WRAP_RANGE(m, BelPin, wrap_context<BelPin>);
|
||||
|
||||
WRAP_MAP_UPTR(m, CellMap, "IdCellMap");
|
||||
WRAP_MAP_UPTR(m, NetMap, "IdNetMap");
|
||||
WRAP_MAP(m, HierarchyMap, wrap_context<HierarchicalCell &>, "HierarchyMap");
|
||||
}
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
|
||||
#endif // NO_PYTHON
|
||||
97
fpga_interchange/arch_pybindings.h
Normal file
97
fpga_interchange/arch_pybindings.h
Normal file
@ -0,0 +1,97 @@
|
||||
/*
|
||||
* nextpnr -- Next Generation Place and Route
|
||||
*
|
||||
* Copyright (C) 2020 David Shah <dave@ds0.me>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
#ifndef ARCH_PYBINDINGS_H
|
||||
#define ARCH_PYBINDINGS_H
|
||||
#ifndef NO_PYTHON
|
||||
|
||||
#include "nextpnr.h"
|
||||
#include "pybindings.h"
|
||||
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
namespace PythonConversion {
|
||||
|
||||
template <> struct string_converter<BelId>
|
||||
{
|
||||
BelId from_str(Context *ctx, std::string name) { return ctx->getBelByName(ctx->id(name)); }
|
||||
|
||||
std::string to_str(Context *ctx, BelId id)
|
||||
{
|
||||
if (id == BelId())
|
||||
throw bad_wrap();
|
||||
return ctx->getBelName(id).str(ctx);
|
||||
}
|
||||
};
|
||||
|
||||
template <> struct string_converter<WireId>
|
||||
{
|
||||
WireId from_str(Context *ctx, std::string name) { return ctx->getWireByName(ctx->id(name)); }
|
||||
|
||||
std::string to_str(Context *ctx, WireId id)
|
||||
{
|
||||
if (id == WireId())
|
||||
throw bad_wrap();
|
||||
return ctx->getWireName(id).str(ctx);
|
||||
}
|
||||
};
|
||||
|
||||
template <> struct string_converter<const WireId>
|
||||
{
|
||||
WireId from_str(Context *ctx, std::string name) { return ctx->getWireByName(ctx->id(name)); }
|
||||
|
||||
std::string to_str(Context *ctx, WireId id)
|
||||
{
|
||||
if (id == WireId())
|
||||
throw bad_wrap();
|
||||
return ctx->getWireName(id).str(ctx);
|
||||
}
|
||||
};
|
||||
|
||||
template <> struct string_converter<PipId>
|
||||
{
|
||||
PipId from_str(Context *ctx, std::string name) { return ctx->getPipByName(ctx->id(name)); }
|
||||
|
||||
std::string to_str(Context *ctx, PipId id)
|
||||
{
|
||||
if (id == PipId())
|
||||
throw bad_wrap();
|
||||
return ctx->getPipName(id).str(ctx);
|
||||
}
|
||||
};
|
||||
|
||||
template <> struct string_converter<BelPin>
|
||||
{
|
||||
BelPin from_str(Context *ctx, std::string name)
|
||||
{
|
||||
NPNR_ASSERT_FALSE("string_converter<BelPin>::from_str not implemented");
|
||||
}
|
||||
|
||||
std::string to_str(Context *ctx, BelPin pin)
|
||||
{
|
||||
if (pin.bel == BelId())
|
||||
throw bad_wrap();
|
||||
return ctx->getBelName(pin.bel).str(ctx) + "/" + pin.pin.str(ctx);
|
||||
}
|
||||
};
|
||||
|
||||
} // namespace PythonConversion
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
#endif
|
||||
#endif
|
||||
189
fpga_interchange/archdefs.h
Normal file
189
fpga_interchange/archdefs.h
Normal file
@ -0,0 +1,189 @@
|
||||
/*
|
||||
* nextpnr -- Next Generation Place and Route
|
||||
*
|
||||
* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef NEXTPNR_H
|
||||
#error Include "archdefs.h" via "nextpnr.h" only.
|
||||
#endif
|
||||
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
#include <cstdint>
|
||||
|
||||
typedef int delay_t;
|
||||
|
||||
struct DelayInfo
|
||||
{
|
||||
delay_t delay = 0;
|
||||
|
||||
delay_t minRaiseDelay() const { return delay; }
|
||||
delay_t maxRaiseDelay() const { return delay; }
|
||||
|
||||
delay_t minFallDelay() const { return delay; }
|
||||
delay_t maxFallDelay() const { return delay; }
|
||||
|
||||
delay_t minDelay() const { return delay; }
|
||||
delay_t maxDelay() const { return delay; }
|
||||
|
||||
DelayInfo operator+(const DelayInfo &other) const
|
||||
{
|
||||
DelayInfo ret;
|
||||
ret.delay = this->delay + other.delay;
|
||||
return ret;
|
||||
}
|
||||
};
|
||||
|
||||
// -----------------------------------------------------------------------
|
||||
|
||||
// https://bugreports.qt.io/browse/QTBUG-80789
|
||||
|
||||
#ifndef Q_MOC_RUN
|
||||
|
||||
enum ConstIds
|
||||
{
|
||||
ID_NONE
|
||||
#define X(t) , ID_##t
|
||||
#include "constids.inc"
|
||||
#undef X
|
||||
};
|
||||
|
||||
#define X(t) static constexpr auto id_##t = IdString(ID_##t);
|
||||
#include "constids.inc"
|
||||
#undef X
|
||||
|
||||
#endif
|
||||
|
||||
struct BelId
|
||||
{
|
||||
// Tile that contains this BEL.
|
||||
int32_t tile = -1;
|
||||
// Index into tile type BEL array.
|
||||
// BEL indicies are the same for all tiles of the same type.
|
||||
int32_t index = -1;
|
||||
|
||||
bool operator==(const BelId &other) const { return tile == other.tile && index == other.index; }
|
||||
bool operator!=(const BelId &other) const { return tile != other.tile || index != other.index; }
|
||||
bool operator<(const BelId &other) const
|
||||
{
|
||||
return tile < other.tile || (tile == other.tile && index < other.index);
|
||||
}
|
||||
};
|
||||
|
||||
struct WireId
|
||||
{
|
||||
// Tile that contains this wire.
|
||||
int32_t tile = -1;
|
||||
int32_t index = -1;
|
||||
|
||||
bool operator==(const WireId &other) const { return tile == other.tile && index == other.index; }
|
||||
bool operator!=(const WireId &other) const { return tile != other.tile || index != other.index; }
|
||||
bool operator<(const WireId &other) const
|
||||
{
|
||||
return tile < other.tile || (tile == other.tile && index < other.index);
|
||||
}
|
||||
};
|
||||
|
||||
struct PipId
|
||||
{
|
||||
int32_t tile = -1;
|
||||
int32_t index = -1;
|
||||
|
||||
bool operator==(const PipId &other) const { return tile == other.tile && index == other.index; }
|
||||
bool operator!=(const PipId &other) const { return tile != other.tile || index != other.index; }
|
||||
bool operator<(const PipId &other) const
|
||||
{
|
||||
return tile < other.tile || (tile == other.tile && index < other.index);
|
||||
}
|
||||
};
|
||||
|
||||
struct GroupId
|
||||
{
|
||||
bool operator==(const GroupId &other) const { return true; }
|
||||
bool operator!=(const GroupId &other) const { return false; }
|
||||
};
|
||||
|
||||
struct DecalId
|
||||
{
|
||||
bool operator==(const DecalId &other) const { return true; }
|
||||
bool operator!=(const DecalId &other) const { return false; }
|
||||
};
|
||||
|
||||
struct ArchNetInfo
|
||||
{
|
||||
};
|
||||
|
||||
struct NetInfo;
|
||||
|
||||
struct ArchCellInfo
|
||||
{
|
||||
};
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
|
||||
namespace std {
|
||||
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX BelId>
|
||||
{
|
||||
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX BelId &bel) const noexcept
|
||||
{
|
||||
std::size_t seed = 0;
|
||||
boost::hash_combine(seed, hash<int>()(bel.tile));
|
||||
boost::hash_combine(seed, hash<int>()(bel.index));
|
||||
return seed;
|
||||
}
|
||||
};
|
||||
|
||||
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX WireId>
|
||||
{
|
||||
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX WireId &wire) const noexcept
|
||||
{
|
||||
std::size_t seed = 0;
|
||||
boost::hash_combine(seed, hash<int>()(wire.tile));
|
||||
boost::hash_combine(seed, hash<int>()(wire.index));
|
||||
return seed;
|
||||
}
|
||||
};
|
||||
|
||||
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX PipId>
|
||||
{
|
||||
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX PipId &pip) const noexcept
|
||||
{
|
||||
std::size_t seed = 0;
|
||||
boost::hash_combine(seed, hash<int>()(pip.tile));
|
||||
boost::hash_combine(seed, hash<int>()(pip.index));
|
||||
return seed;
|
||||
}
|
||||
};
|
||||
|
||||
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX GroupId>
|
||||
{
|
||||
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX GroupId &group) const noexcept
|
||||
{
|
||||
std::size_t seed = 0;
|
||||
return seed;
|
||||
}
|
||||
};
|
||||
|
||||
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX DecalId>
|
||||
{
|
||||
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX DecalId &decal) const noexcept
|
||||
{
|
||||
std::size_t seed = 0;
|
||||
return seed;
|
||||
}
|
||||
};
|
||||
} // namespace std
|
||||
0
fpga_interchange/constids.inc
Normal file
0
fpga_interchange/constids.inc
Normal file
0
fpga_interchange/family.cmake
Normal file
0
fpga_interchange/family.cmake
Normal file
87
fpga_interchange/fpga_interchange_archdefs.h
Normal file
87
fpga_interchange/fpga_interchange_archdefs.h
Normal file
@ -0,0 +1,87 @@
|
||||
#include <cstdint>
|
||||
|
||||
typedef int delay_t;
|
||||
|
||||
struct DelayInfo
|
||||
{
|
||||
delay_t delay = 0;
|
||||
|
||||
delay_t minRaiseDelay() const { return delay; }
|
||||
delay_t maxRaiseDelay() const { return delay; }
|
||||
|
||||
delay_t minFallDelay() const { return delay; }
|
||||
delay_t maxFallDelay() const { return delay; }
|
||||
|
||||
delay_t minDelay() const { return delay; }
|
||||
delay_t maxDelay() const { return delay; }
|
||||
|
||||
DelayInfo operator+(const DelayInfo &other) const
|
||||
{
|
||||
DelayInfo ret;
|
||||
ret.delay = this->delay + other.delay;
|
||||
return ret;
|
||||
}
|
||||
};
|
||||
|
||||
struct BelId
|
||||
{
|
||||
// Tile that contains this BEL.
|
||||
int32_t tile = -1;
|
||||
// Index into tile type BEL array.
|
||||
// BEL indicies are the same for all tiles of the same type.
|
||||
int32_t index = -1;
|
||||
|
||||
bool operator==(const BelId &other) const { return tile == other.tile && index == other.index; }
|
||||
bool operator!=(const BelId &other) const { return tile != other.tile || index != other.index; }
|
||||
bool operator<(const BelId &other) const
|
||||
{
|
||||
return tile < other.tile || (tile == other.tile && index < other.index);
|
||||
}
|
||||
};
|
||||
|
||||
struct WireId
|
||||
{
|
||||
// Tile that contains this wire.
|
||||
int32_t tile = -1;
|
||||
int32_t index = -1;
|
||||
|
||||
bool operator==(const WireId &other) const { return tile == other.tile && index == other.index; }
|
||||
bool operator!=(const WireId &other) const { return tile != other.tile || index != other.index; }
|
||||
bool operator<(const WireId &other) const
|
||||
{
|
||||
return tile < other.tile || (tile == other.tile && index < other.index);
|
||||
}
|
||||
};
|
||||
|
||||
struct PipId
|
||||
{
|
||||
int32_t tile = -1;
|
||||
int32_t index = -1;
|
||||
|
||||
bool operator==(const PipId &other) const { return tile == other.tile && index == other.index; }
|
||||
bool operator!=(const PipId &other) const { return tile != other.tile || index != other.index; }
|
||||
bool operator<(const PipId &other) const
|
||||
{
|
||||
return tile < other.tile || (tile == other.tile && index < other.index);
|
||||
}
|
||||
};
|
||||
|
||||
struct GroupId
|
||||
{
|
||||
};
|
||||
|
||||
struct DecalId
|
||||
{
|
||||
};
|
||||
|
||||
struct ArchNetInfo
|
||||
{
|
||||
};
|
||||
|
||||
struct NetInfo
|
||||
{
|
||||
};
|
||||
|
||||
struct ArchCellInfo
|
||||
{
|
||||
};
|
||||
85
fpga_interchange/main.cc
Normal file
85
fpga_interchange/main.cc
Normal file
@ -0,0 +1,85 @@
|
||||
/*
|
||||
* nextpnr -- Next Generation Place and Route
|
||||
*
|
||||
* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifdef MAIN_EXECUTABLE
|
||||
|
||||
#include <fstream>
|
||||
#include "command.h"
|
||||
#include "design_utils.h"
|
||||
#include "jsonwrite.h"
|
||||
#include "log.h"
|
||||
#include "timing.h"
|
||||
|
||||
USING_NEXTPNR_NAMESPACE
|
||||
|
||||
class FpgaInterchangeCommandHandler : public CommandHandler
|
||||
{
|
||||
public:
|
||||
FpgaInterchangeCommandHandler(int argc, char **argv);
|
||||
virtual ~FpgaInterchangeCommandHandler(){};
|
||||
std::unique_ptr<Context> createContext(std::unordered_map<std::string, Property> &values) override;
|
||||
void setupArchContext(Context *ctx) override{};
|
||||
void customBitstream(Context *ctx) override;
|
||||
void customAfterLoad(Context *ctx) override;
|
||||
|
||||
protected:
|
||||
po::options_description getArchOptions() override;
|
||||
};
|
||||
|
||||
FpgaInterchangeCommandHandler::FpgaInterchangeCommandHandler(int argc, char **argv) : CommandHandler(argc, argv) {}
|
||||
|
||||
po::options_description FpgaInterchangeCommandHandler::getArchOptions()
|
||||
{
|
||||
po::options_description specific("Architecture specific options");
|
||||
specific.add_options()("chipdb", po::value<std::string>(), "name of chip database binary");
|
||||
specific.add_options()("xdc", po::value<std::vector<std::string>>(), "XDC-style constraints file");
|
||||
specific.add_options()("phys", po::value<std::string>(), "FPGA interchange Physical netlist to write");
|
||||
|
||||
return specific;
|
||||
}
|
||||
|
||||
void FpgaInterchangeCommandHandler::customBitstream(Context *ctx)
|
||||
{
|
||||
if (vm.count("phys")) {
|
||||
std::string filename = vm["phys"].as<std::string>();
|
||||
ctx->writePhysicalNetlist(filename);
|
||||
}
|
||||
}
|
||||
|
||||
std::unique_ptr<Context> FpgaInterchangeCommandHandler::createContext(std::unordered_map<std::string, Property> &values)
|
||||
{
|
||||
ArchArgs chipArgs;
|
||||
if (!vm.count("chipdb")) {
|
||||
log_error("chip database binary must be provided\n");
|
||||
}
|
||||
chipArgs.chipdb = vm["chipdb"].as<std::string>();
|
||||
return std::unique_ptr<Context>(new Context(chipArgs));
|
||||
}
|
||||
|
||||
void FpgaInterchangeCommandHandler::customAfterLoad(Context *ctx)
|
||||
{
|
||||
}
|
||||
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
FpgaInterchangeCommandHandler handler(argc, argv);
|
||||
return handler.exec();
|
||||
}
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user