{SLICEL,SLICEM} -> QUARTER_SLICE
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xc7/arch.cc
49
xc7/arch.cc
@ -36,6 +36,7 @@ NEXTPNR_NAMESPACE_BEGIN
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const DDB *torc = nullptr;
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const Sites *torc_sites = nullptr;
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const Tiles *torc_tiles = nullptr;
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std::vector<IdString> bel_index_to_type;
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// -----------------------------------------------------------------------
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@ -71,6 +72,17 @@ Arch::Arch(ArchArgs args) : args(args)
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torc_sites = &torc->getSites();
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torc_tiles = &torc->getTiles();
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bel_index_to_type.resize(torc_sites->getSiteCount());
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for (SiteIndex i(0); i < torc_sites->getSiteCount(); ++i) {
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const auto& s = torc_sites->getSite(i);
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auto pd = s.getPrimitiveDefPtr();
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const auto& type = pd->getName();
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if (type == "SLICEL" || type == "SLICEM")
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bel_index_to_type[i] = id_QUARTER_SLICE;
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else
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bel_index_to_type[i] = id(type);
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}
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bel_to_cell.resize(torc_sites->getSiteCount());
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}
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@ -115,6 +127,15 @@ BelId Arch::getBelByLocation(Loc loc) const
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for (SiteIndex i(0); i < torc_sites->getSiteCount(); ++i) {
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BelId b;
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b.index = i;
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if (bel_index_to_type[i] == id_QUARTER_SLICE) {
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b.pos = BelId::A;
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bel_by_loc[getBelLocation(b)] = b;
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b.pos = BelId::B;
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bel_by_loc[getBelLocation(b)] = b;
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b.pos = BelId::C;
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bel_by_loc[getBelLocation(b)] = b;
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b.pos = BelId::D;
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}
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bel_by_loc[getBelLocation(b)] = b;
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}
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}
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@ -130,12 +151,14 @@ BelRange Arch::getBelsByTile(int x, int y) const
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{
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BelRange br;
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br.b.cursor = std::next(torc_sites->getSites().begin(), Arch::getBelByLocation(Loc(x, y, 0)).index);
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br.e.cursor = br.b.cursor;
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auto b = getBelByLocation(Loc(x, y, 0));
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br.b.index = b.index;
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br.b.pos = b.pos;
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br.e = br.b;
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if (br.e.cursor != torc_sites->getSites().end()) {
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while (br.e.cursor < torc_sites->getSites().end() && torc_sites->getSite((*br.e).index).getTileIndex() == torc_sites->getSite((*br.b).index).getTileIndex())
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br.e.cursor++;
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if (br.e.index != SiteIndex(torc_sites->getSiteCount())) {
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while (br.e.index < SiteIndex(torc_sites->getSiteCount()) && torc_sites->getSite((*br.e).index).getTileIndex() == torc_sites->getSite((*br.b).index).getTileIndex())
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br.e++;
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}
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return br;
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@ -674,7 +697,7 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
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bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
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{
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if (cell->type == id_SLICEL)
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if (cell->type == id_QUARTER_SLICE)
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{
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if (fromPort.index >= id_A1.index && fromPort.index <= id_A6.index)
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return toPort == id_A || toPort == id_AQ;
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@ -689,7 +712,7 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
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// Get the port class, also setting clockPort to associated clock if applicable
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TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockPort) const
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{
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if (cell->type == id_SLICEL) {
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if (cell->type == id_QUARTER_SLICE) {
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if (port == id_CLK)
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return TMG_CLOCK_INPUT;
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if (port == id_CIN)
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@ -754,7 +777,7 @@ void Arch::assignArchInfo()
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void Arch::assignCellInfo(CellInfo *cell)
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{
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cell->belType = cell->type;
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if (cell->type == id_SLICEL) {
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if (cell->type == id_QUARTER_SLICE) {
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cell->lcInfo.dffEnable = bool_or_default(cell->params, id_DFF_ENABLE);
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cell->lcInfo.carryEnable = bool_or_default(cell->params, id_CARRY_ENABLE);
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cell->lcInfo.negClk = bool_or_default(cell->params, id_NEG_CLK);
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@ -773,4 +796,14 @@ void Arch::assignCellInfo(CellInfo *cell)
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}
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}
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void operator++(BelId::bel &b) {
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switch (b) {
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case BelId::A: b = BelId::B; return;
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case BelId::B: b = BelId::C; return;
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case BelId::C: b = BelId::D; return;
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default: break;
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}
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throw;
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}
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NEXTPNR_NAMESPACE_END
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39
xc7/arch.h
39
xc7/arch.h
@ -236,36 +236,41 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD {
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extern const DDB *torc;
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extern const Sites *torc_sites;
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extern const Tiles *torc_tiles;
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extern std::vector<IdString> bel_index_to_type;
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/************************ End of chipdb section. ************************/
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struct BelIterator
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struct BelIterator : public BelId
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{
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Array<const Site>::iterator cursor;
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BelIterator operator++()
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{
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cursor++;
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if (bel_index_to_type[index] == id_QUARTER_SLICE) {
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if (pos < D) {
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++pos;
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return *this;
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}
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}
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if (bel_index_to_type[++index] == id_QUARTER_SLICE)
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pos = A;
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else
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pos = NOT_APPLICABLE;
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return *this;
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}
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BelIterator operator++(int)
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{
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BelIterator prior(*this);
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cursor++;
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operator++();
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return prior;
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}
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bool operator!=(const BelIterator &other) const { return cursor != other.cursor; }
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bool operator!=(const BelIterator &other) const { return BelId::operator!=(other); }
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bool operator==(const BelIterator &other) const { return cursor == other.cursor; }
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bool operator==(const BelIterator &other) const { return BelId::operator==(other); }
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BelId operator*() const
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{
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BelId ret;
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ret.index = SiteIndex(std::distance(torc_sites->getSites().begin(), cursor));
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return ret;
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}
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BelId operator*() const { return *this; }
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};
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struct BelRange
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@ -472,8 +477,8 @@ struct Arch : BaseCtx
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BelRange getBels() const
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{
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BelRange range;
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range.b.cursor = torc_sites->getSites().begin();
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range.e.cursor = torc_sites->getSites().end();
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range.b.index = SiteIndex(0);
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range.e.index = SiteIndex(torc_sites->getSiteCount());
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return range;
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}
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@ -496,9 +501,7 @@ struct Arch : BaseCtx
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IdString getBelType(BelId bel) const
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{
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NPNR_ASSERT(bel != BelId());
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const auto& site = torc_sites->getSite(bel.index);
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auto prim_def = site.getPrimitiveDefPtr();
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return id(prim_def->getName());
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return bel_index_to_type[bel.index];
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}
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WireId getBelPinWire(BelId bel, IdString pin) const;
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@ -67,10 +67,12 @@ enum ConstIds
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struct BelId
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{
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SiteIndex index = SiteIndex(-1);
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enum bel : int8_t { NOT_APPLICABLE, A, B, C, D } pos = NOT_APPLICABLE;
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bool operator==(const BelId &other) const { return index == other.index; }
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bool operator!=(const BelId &other) const { return index != other.index; }
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bool operator==(const BelId &other) const { return index == other.index && pos == pos; }
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bool operator!=(const BelId &other) const { return index != other.index || pos != pos; }
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};
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void operator++(BelId::bel &b);
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struct WireId
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{
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@ -43,7 +43,7 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri
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}
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new_cell->type = type;
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if (type == ctx->id("XC7_LC")) {
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new_cell->type = id_SLICEL; // HACK HACK HACK: Place one LC into each slice
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new_cell->type = id_QUARTER_SLICE; // HACK HACK HACK: Place one LC into each slice
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new_cell->params[ctx->id("LUT_INIT")] = "0";
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new_cell->params[ctx->id("NEG_CLK")] = "0";
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new_cell->params[ctx->id("CARRY_ENABLE")] = "0";
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@ -464,7 +464,7 @@ X(FDCE)
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X(FDPE)
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X(BUFGCTRL)
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X(SLICEL)
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X(QUARTER_SLICE)
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X(IOBUF)
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X(IOB33S)
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X(IOB33M) // What is the difference between IOB33S and IOB33M?
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