Finishes placement now
This commit is contained in:
parent
32f5346378
commit
57c273898c
95
xc7/arch.cc
95
xc7/arch.cc
@ -173,6 +173,9 @@ WireId Arch::getBelPinWire(BelId bel, IdString pin) const
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{
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WireId ret;
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const auto& site = ddbSites->getSite(bel.index);
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ret.index = site.getPinTilewire(pin.str(this));
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// NPNR_ASSERT(bel != BelId());
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//
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// int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
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@ -229,9 +232,9 @@ WireId Arch::getWireByName(IdString name) const
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wire_by_name[id(chip_info->wire_data[i].name.get())] = i;
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}
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auto it = wire_by_name.find(name);
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if (it != wire_by_name.end())
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ret.index = it->second;
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//auto it = wire_by_name.find(name);
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//if (it != wire_by_name.end())
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// ret.index = it->second;
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return ret;
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}
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@ -239,38 +242,38 @@ WireId Arch::getWireByName(IdString name) const
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IdString Arch::getWireType(WireId wire) const
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{
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NPNR_ASSERT(wire != WireId());
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switch (chip_info->wire_data[wire.index].type) {
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case WireInfoPOD::WIRE_TYPE_NONE:
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return IdString();
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case WireInfoPOD::WIRE_TYPE_GLB2LOCAL:
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return id("GLB2LOCAL");
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case WireInfoPOD::WIRE_TYPE_GLB_NETWK:
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return id("GLB_NETWK");
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case WireInfoPOD::WIRE_TYPE_LOCAL:
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return id("LOCAL");
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case WireInfoPOD::WIRE_TYPE_LUTFF_IN:
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return id("LUTFF_IN");
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case WireInfoPOD::WIRE_TYPE_LUTFF_IN_LUT:
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return id("LUTFF_IN_LUT");
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case WireInfoPOD::WIRE_TYPE_LUTFF_LOUT:
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return id("LUTFF_LOUT");
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case WireInfoPOD::WIRE_TYPE_LUTFF_OUT:
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return id("LUTFF_OUT");
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case WireInfoPOD::WIRE_TYPE_LUTFF_COUT:
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return id("LUTFF_COUT");
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case WireInfoPOD::WIRE_TYPE_LUTFF_GLOBAL:
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return id("LUTFF_GLOBAL");
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case WireInfoPOD::WIRE_TYPE_CARRY_IN_MUX:
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return id("CARRY_IN_MUX");
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case WireInfoPOD::WIRE_TYPE_SP4_V:
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return id("SP4_V");
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case WireInfoPOD::WIRE_TYPE_SP4_H:
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return id("SP4_H");
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case WireInfoPOD::WIRE_TYPE_SP12_V:
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return id("SP12_V");
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case WireInfoPOD::WIRE_TYPE_SP12_H:
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return id("SP12_H");
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}
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// switch (chip_info->wire_data[wire.index].type) {
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// case WireInfoPOD::WIRE_TYPE_NONE:
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// return IdString();
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// case WireInfoPOD::WIRE_TYPE_GLB2LOCAL:
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// return id("GLB2LOCAL");
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// case WireInfoPOD::WIRE_TYPE_GLB_NETWK:
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// return id("GLB_NETWK");
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// case WireInfoPOD::WIRE_TYPE_LOCAL:
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// return id("LOCAL");
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// case WireInfoPOD::WIRE_TYPE_LUTFF_IN:
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// return id("LUTFF_IN");
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// case WireInfoPOD::WIRE_TYPE_LUTFF_IN_LUT:
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// return id("LUTFF_IN_LUT");
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// case WireInfoPOD::WIRE_TYPE_LUTFF_LOUT:
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// return id("LUTFF_LOUT");
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// case WireInfoPOD::WIRE_TYPE_LUTFF_OUT:
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// return id("LUTFF_OUT");
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// case WireInfoPOD::WIRE_TYPE_LUTFF_COUT:
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// return id("LUTFF_COUT");
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// case WireInfoPOD::WIRE_TYPE_LUTFF_GLOBAL:
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// return id("LUTFF_GLOBAL");
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// case WireInfoPOD::WIRE_TYPE_CARRY_IN_MUX:
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// return id("CARRY_IN_MUX");
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// case WireInfoPOD::WIRE_TYPE_SP4_V:
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// return id("SP4_V");
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// case WireInfoPOD::WIRE_TYPE_SP4_H:
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// return id("SP4_H");
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// case WireInfoPOD::WIRE_TYPE_SP12_V:
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// return id("SP12_V");
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// case WireInfoPOD::WIRE_TYPE_SP12_H:
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// return id("SP12_H");
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// }
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return IdString();
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}
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@ -507,8 +510,8 @@ DecalXY Arch::getWireDecal(WireId wire) const
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{
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DecalXY decalxy;
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decalxy.decal.type = DecalId::TYPE_WIRE;
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decalxy.decal.index = wire.index;
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decalxy.decal.active = wire_to_net.at(wire.index) != nullptr;
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//decalxy.decal.index = wire.index;
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//decalxy.decal.active = wire_to_net.at(wire.index) != nullptr;
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return decalxy;
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}
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@ -671,6 +674,15 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
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bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
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{
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if (cell->type == id_SLICEL)
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{
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if (fromPort.index >= id_A1.index && fromPort.index <= id_A6.index)
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return toPort == id_A || toPort == id_AQ;
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}
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else if (cell->type == id_BUFGCTRL)
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{
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return true;
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}
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return false;
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}
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@ -682,19 +694,16 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id
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return TMG_CLOCK_INPUT;
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if (port == id_CIN)
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return TMG_COMB_INPUT;
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if (port == id_COUT || port == id_O)
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if (port == id_COUT || port == id_A)
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return TMG_COMB_OUTPUT;
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if (cell->lcInfo.dffEnable) {
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clockPort = id_CLK;
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if (port == id_OQ)
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if (port == id_AQ)
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return TMG_REGISTER_OUTPUT;
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else
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return TMG_REGISTER_INPUT;
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} else {
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if (port == id_O)
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return TMG_COMB_OUTPUT;
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else
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return TMG_COMB_INPUT;
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return TMG_COMB_INPUT;
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}
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// TODO
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//if (port == id_OMUX)
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95
xc7/arch.h
95
xc7/arch.h
@ -305,10 +305,11 @@ struct BelPinRange
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struct WireIterator
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{
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int cursor = -1;
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Tilewire cursor;
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void operator++() { cursor++; }
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bool operator!=(const WireIterator &other) const { return cursor != other.cursor; }
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// TODO
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void operator++() { /*cursor++;*/ }
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bool operator!=(const WireIterator &other) const { return !(cursor == other.cursor); }
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WireId operator*() const
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{
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@ -511,18 +512,19 @@ struct Arch : BaseCtx
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IdString getWireName(WireId wire) const
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{
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NPNR_ASSERT(wire != WireId());
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return id(chip_info->wire_data[wire.index].name.get());
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//return id(chip_info->wire_data[wire.index].name.get());
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return IdString();
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}
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IdString getWireType(WireId wire) const;
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uint32_t getWireChecksum(WireId wire) const { return wire.index; }
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uint32_t getWireChecksum(WireId wire) const { return hash_value(wire.index); }
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void bindWire(WireId wire, NetInfo *net, PlaceStrength strength)
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{
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NPNR_ASSERT(wire != WireId());
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NPNR_ASSERT(wire_to_net[wire.index] == nullptr);
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wire_to_net[wire.index] = net;
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//NPNR_ASSERT(wire_to_net[wire.index] == nullptr);
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//wire_to_net[wire.index] = net;
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net->wires[wire].pip = PipId();
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net->wires[wire].strength = strength;
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refreshUiWire(wire);
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@ -531,49 +533,52 @@ struct Arch : BaseCtx
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void unbindWire(WireId wire)
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{
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NPNR_ASSERT(wire != WireId());
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NPNR_ASSERT(wire_to_net[wire.index] != nullptr);
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//NPNR_ASSERT(wire_to_net[wire.index] != nullptr);
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auto &net_wires = wire_to_net[wire.index]->wires;
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auto it = net_wires.find(wire);
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NPNR_ASSERT(it != net_wires.end());
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//auto &net_wires = wire_to_net[wire.index]->wires;
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//auto it = net_wires.find(wire);
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//NPNR_ASSERT(it != net_wires.end());
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auto pip = it->second.pip;
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if (pip != PipId()) {
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pip_to_net[pip.index] = nullptr;
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switches_locked[chip_info->pip_data[pip.index].switch_index] = nullptr;
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}
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//auto pip = it->second.pip;
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//if (pip != PipId()) {
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// pip_to_net[pip.index] = nullptr;
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// switches_locked[chip_info->pip_data[pip.index].switch_index] = nullptr;
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//}
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net_wires.erase(it);
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wire_to_net[wire.index] = nullptr;
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//net_wires.erase(it);
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//wire_to_net[wire.index] = nullptr;
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refreshUiWire(wire);
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}
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bool checkWireAvail(WireId wire) const
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{
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NPNR_ASSERT(wire != WireId());
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return wire_to_net[wire.index] == nullptr;
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//NPNR_ASSERT(wire != WireId());
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//return wire_to_net[wire.index] == nullptr;
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return true;
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}
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NetInfo *getBoundWireNet(WireId wire) const
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{
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NPNR_ASSERT(wire != WireId());
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return wire_to_net[wire.index];
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//NPNR_ASSERT(wire != WireId());
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//return wire_to_net[wire.index];
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return nullptr;
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}
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NetInfo *getConflictingWireNet(WireId wire) const
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{
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NPNR_ASSERT(wire != WireId());
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return wire_to_net[wire.index];
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//NPNR_ASSERT(wire != WireId());
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//return wire_to_net[wire.index];
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return nullptr;
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}
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DelayInfo getWireDelay(WireId wire) const
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{
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DelayInfo delay;
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NPNR_ASSERT(wire != WireId());
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if (fast_part)
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delay.delay = chip_info->wire_data[wire.index].fast_delay;
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else
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delay.delay = chip_info->wire_data[wire.index].slow_delay;
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//NPNR_ASSERT(wire != WireId());
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//if (fast_part)
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// delay.delay = chip_info->wire_data[wire.index].fast_delay;
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//else
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// delay.delay = chip_info->wire_data[wire.index].slow_delay;
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return delay;
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}
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@ -589,8 +594,8 @@ struct Arch : BaseCtx
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WireRange getWires() const
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{
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WireRange range;
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range.b.cursor = 0;
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range.e.cursor = 0; //chip_info->num_wires;
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//range.b.cursor = 0;
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//range.e.cursor = chip_info->num_wires;
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return range;
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}
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@ -608,11 +613,11 @@ struct Arch : BaseCtx
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switches_locked[chip_info->pip_data[pip.index].switch_index] = net;
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WireId dst;
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dst.index = chip_info->pip_data[pip.index].dst;
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NPNR_ASSERT(wire_to_net[dst.index] == nullptr);
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wire_to_net[dst.index] = net;
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net->wires[dst].pip = pip;
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net->wires[dst].strength = strength;
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//dst.index = chip_info->pip_data[pip.index].dst;
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//NPNR_ASSERT(wire_to_net[dst.index] == nullptr);
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//wire_to_net[dst.index] = net;
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//net->wires[dst].pip = pip;
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//net->wires[dst].strength = strength;
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refreshUiPip(pip);
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refreshUiWire(dst);
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}
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@ -624,9 +629,9 @@ struct Arch : BaseCtx
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NPNR_ASSERT(switches_locked[chip_info->pip_data[pip.index].switch_index] != nullptr);
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WireId dst;
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dst.index = chip_info->pip_data[pip.index].dst;
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NPNR_ASSERT(wire_to_net[dst.index] != nullptr);
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wire_to_net[dst.index] = nullptr;
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//dst.index = chip_info->pip_data[pip.index].dst;
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//NPNR_ASSERT(wire_to_net[dst.index] != nullptr);
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//wire_to_net[dst.index] = nullptr;
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pip_to_net[pip.index]->wires.erase(dst);
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pip_to_net[pip.index] = nullptr;
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@ -698,7 +703,7 @@ struct Arch : BaseCtx
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{
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WireId wire;
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NPNR_ASSERT(pip != PipId());
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wire.index = chip_info->pip_data[pip.index].src;
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//wire.index = chip_info->pip_data[pip.index].src;
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return wire;
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}
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@ -706,7 +711,7 @@ struct Arch : BaseCtx
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{
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WireId wire;
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NPNR_ASSERT(pip != PipId());
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wire.index = chip_info->pip_data[pip.index].dst;
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//wire.index = chip_info->pip_data[pip.index].dst;
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return wire;
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}
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@ -725,8 +730,8 @@ struct Arch : BaseCtx
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{
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PipRange range;
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NPNR_ASSERT(wire != WireId());
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range.b.cursor = chip_info->wire_data[wire.index].pips_downhill.get();
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range.e.cursor = range.b.cursor + chip_info->wire_data[wire.index].num_downhill;
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//range.b.cursor = chip_info->wire_data[wire.index].pips_downhill.get();
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//range.e.cursor = range.b.cursor + chip_info->wire_data[wire.index].num_downhill;
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return range;
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}
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@ -734,8 +739,8 @@ struct Arch : BaseCtx
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{
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PipRange range;
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NPNR_ASSERT(wire != WireId());
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range.b.cursor = chip_info->wire_data[wire.index].pips_uphill.get();
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range.e.cursor = range.b.cursor + chip_info->wire_data[wire.index].num_uphill;
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//range.b.cursor = chip_info->wire_data[wire.index].pips_uphill.get();
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//range.e.cursor = range.b.cursor + chip_info->wire_data[wire.index].num_uphill;
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return range;
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}
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@ -22,6 +22,7 @@
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#endif
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#include "torc/Architecture.hpp"
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using namespace torc::architecture;
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using namespace torc::architecture::xilinx;
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NEXTPNR_NAMESPACE_BEGIN
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@ -73,10 +74,10 @@ struct BelId
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struct WireId
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{
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int32_t index = -1;
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Tilewire index;
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bool operator==(const WireId &other) const { return index == other.index; }
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bool operator!=(const WireId &other) const { return index != other.index; }
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bool operator!=(const WireId &other) const { return !(index == other.index); }
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};
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struct PipId
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@ -163,7 +164,7 @@ template <> struct hash<NEXTPNR_NAMESPACE_PREFIX WireId>
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{
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std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX WireId &wire) const noexcept
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{
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return hash<int>()(wire.index);
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return hash_value(wire.index);
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}
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};
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36
xc7/cells.cc
36
xc7/cells.cc
@ -53,21 +53,21 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri
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new_cell->params[ctx->id("CIN_CONST")] = "0";
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new_cell->params[ctx->id("CIN_SET")] = "0";
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add_port(ctx, new_cell.get(), "I0", PORT_IN);
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add_port(ctx, new_cell.get(), "I1", PORT_IN);
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add_port(ctx, new_cell.get(), "I2", PORT_IN);
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add_port(ctx, new_cell.get(), "I3", PORT_IN);
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add_port(ctx, new_cell.get(), "I4", PORT_IN);
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add_port(ctx, new_cell.get(), "I5", PORT_IN);
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add_port(ctx, new_cell.get(), "A1", PORT_IN);
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add_port(ctx, new_cell.get(), "A2", PORT_IN);
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add_port(ctx, new_cell.get(), "A3", PORT_IN);
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add_port(ctx, new_cell.get(), "A4", PORT_IN);
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add_port(ctx, new_cell.get(), "A5", PORT_IN);
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add_port(ctx, new_cell.get(), "A6", PORT_IN);
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add_port(ctx, new_cell.get(), "CIN", PORT_IN);
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add_port(ctx, new_cell.get(), "CLK", PORT_IN);
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add_port(ctx, new_cell.get(), "CE", PORT_IN);
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add_port(ctx, new_cell.get(), "SR", PORT_IN);
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add_port(ctx, new_cell.get(), "O", PORT_OUT);
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add_port(ctx, new_cell.get(), "OMUX", PORT_OUT);
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add_port(ctx, new_cell.get(), "OQ", PORT_OUT);
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add_port(ctx, new_cell.get(), "A", PORT_OUT);
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add_port(ctx, new_cell.get(), "AQ", PORT_OUT);
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add_port(ctx, new_cell.get(), "AMUX", PORT_OUT);
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add_port(ctx, new_cell.get(), "COUT", PORT_OUT);
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} else if (type == ctx->id("IOBUF")) {
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new_cell->type = id_IOB33S;
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@ -259,19 +259,19 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri
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void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
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{
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lc->params[ctx->id("LUT_INIT")] = lut->params[ctx->id("LUT_INIT")];
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replace_port(lut, ctx->id("I0"), lc, ctx->id("I0"));
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replace_port(lut, ctx->id("I0"), lc, ctx->id("A1"));
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if (get_net_or_empty(lut, ctx->id("I1")))
|
||||
replace_port(lut, ctx->id("I1"), lc, ctx->id("I1"));
|
||||
replace_port(lut, ctx->id("I1"), lc, ctx->id("A2"));
|
||||
if (get_net_or_empty(lut, ctx->id("I2")))
|
||||
replace_port(lut, ctx->id("I2"), lc, ctx->id("I2"));
|
||||
replace_port(lut, ctx->id("I2"), lc, ctx->id("A3"));
|
||||
if (get_net_or_empty(lut, ctx->id("I3")))
|
||||
replace_port(lut, ctx->id("I3"), lc, ctx->id("I3"));
|
||||
replace_port(lut, ctx->id("I3"), lc, ctx->id("A4"));
|
||||
if (get_net_or_empty(lut, ctx->id("I4")))
|
||||
replace_port(lut, ctx->id("I4"), lc, ctx->id("I3"));
|
||||
replace_port(lut, ctx->id("I4"), lc, ctx->id("A5"));
|
||||
if (get_net_or_empty(lut, ctx->id("I5")))
|
||||
replace_port(lut, ctx->id("I5"), lc, ctx->id("I3"));
|
||||
replace_port(lut, ctx->id("I5"), lc, ctx->id("A6"));
|
||||
if (no_dff) {
|
||||
replace_port(lut, ctx->id("O"), lc, ctx->id("O"));
|
||||
replace_port(lut, ctx->id("O"), lc, ctx->id("A"));
|
||||
lc->params[ctx->id("DFF_ENABLE")] = "0";
|
||||
}
|
||||
}
|
||||
@ -318,10 +318,10 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
|
||||
|
||||
if (pass_thru_lut) {
|
||||
lc->params[ctx->id("LUT_INIT")] = "2";
|
||||
replace_port(dff, ctx->id("D"), lc, ctx->id("I0"));
|
||||
replace_port(dff, ctx->id("D"), lc, ctx->id("A1"));
|
||||
}
|
||||
|
||||
replace_port(dff, ctx->id("Q"), lc, ctx->id("OQ"));
|
||||
replace_port(dff, ctx->id("Q"), lc, ctx->id("AQ"));
|
||||
}
|
||||
|
||||
void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio)
|
||||
|
@ -441,6 +441,16 @@ X(NEG_CLK)
|
||||
|
||||
X(I)
|
||||
|
||||
X(A1)
|
||||
X(A2)
|
||||
X(A3)
|
||||
X(A4)
|
||||
X(A5)
|
||||
X(A6)
|
||||
X(A)
|
||||
X(AQ)
|
||||
X(AMUX)
|
||||
|
||||
X(LUT1)
|
||||
X(LUT2)
|
||||
X(LUT3)
|
||||
|
138
xc7/delay.cc
138
xc7/delay.cc
@ -27,75 +27,75 @@ NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
void ice40DelayFuzzerMain(Context *ctx)
|
||||
{
|
||||
std::vector<WireId> srcWires, dstWires;
|
||||
|
||||
for (int i = 0; i < ctx->chip_info->num_wires; i++) {
|
||||
WireId wire;
|
||||
wire.index = i;
|
||||
|
||||
switch (ctx->chip_info->wire_data[i].type) {
|
||||
case WireInfoPOD::WIRE_TYPE_LUTFF_OUT:
|
||||
srcWires.push_back(wire);
|
||||
break;
|
||||
|
||||
case WireInfoPOD::WIRE_TYPE_LUTFF_IN_LUT:
|
||||
dstWires.push_back(wire);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
ctx->shuffle(srcWires);
|
||||
ctx->shuffle(dstWires);
|
||||
|
||||
int index = 0;
|
||||
int cnt = 0;
|
||||
|
||||
while (cnt < NUM_FUZZ_ROUTES) {
|
||||
if (index >= int(srcWires.size()) || index >= int(dstWires.size())) {
|
||||
index = 0;
|
||||
ctx->shuffle(srcWires);
|
||||
ctx->shuffle(dstWires);
|
||||
}
|
||||
|
||||
WireId src = srcWires[index];
|
||||
WireId dst = dstWires[index++];
|
||||
std::unordered_map<WireId, PipId> route;
|
||||
|
||||
#if NUM_FUZZ_ROUTES <= 1000
|
||||
if (!ctx->getActualRouteDelay(src, dst, nullptr, &route, false))
|
||||
continue;
|
||||
#else
|
||||
if (!ctx->getActualRouteDelay(src, dst, nullptr, &route, true))
|
||||
continue;
|
||||
#endif
|
||||
|
||||
WireId cursor = dst;
|
||||
delay_t delay = 0;
|
||||
|
||||
while (1) {
|
||||
delay += ctx->getWireDelay(cursor).maxDelay();
|
||||
|
||||
printf("%s %d %d %s %s %d %d\n", cursor == dst ? "dst" : "src",
|
||||
int(ctx->chip_info->wire_data[cursor.index].x), int(ctx->chip_info->wire_data[cursor.index].y),
|
||||
ctx->getWireType(cursor).c_str(ctx), ctx->getWireName(cursor).c_str(ctx), int(delay),
|
||||
int(ctx->estimateDelay(cursor, dst)));
|
||||
|
||||
if (cursor == src)
|
||||
break;
|
||||
|
||||
PipId pip = route.at(cursor);
|
||||
delay += ctx->getPipDelay(pip).maxDelay();
|
||||
cursor = ctx->getPipSrcWire(pip);
|
||||
}
|
||||
|
||||
cnt++;
|
||||
|
||||
if (cnt % 100 == 0)
|
||||
fprintf(stderr, "Fuzzed %d arcs.\n", cnt);
|
||||
}
|
||||
// std::vector<WireId> srcWires, dstWires;
|
||||
//
|
||||
// for (int i = 0; i < ctx->chip_info->num_wires; i++) {
|
||||
// WireId wire;
|
||||
// wire.index = i;
|
||||
//
|
||||
// switch (ctx->chip_info->wire_data[i].type) {
|
||||
// case WireInfoPOD::WIRE_TYPE_LUTFF_OUT:
|
||||
// srcWires.push_back(wire);
|
||||
// break;
|
||||
//
|
||||
// case WireInfoPOD::WIRE_TYPE_LUTFF_IN_LUT:
|
||||
// dstWires.push_back(wire);
|
||||
// break;
|
||||
//
|
||||
// default:
|
||||
// break;
|
||||
// }
|
||||
// }
|
||||
//
|
||||
// ctx->shuffle(srcWires);
|
||||
// ctx->shuffle(dstWires);
|
||||
//
|
||||
// int index = 0;
|
||||
// int cnt = 0;
|
||||
//
|
||||
// while (cnt < NUM_FUZZ_ROUTES) {
|
||||
// if (index >= int(srcWires.size()) || index >= int(dstWires.size())) {
|
||||
// index = 0;
|
||||
// ctx->shuffle(srcWires);
|
||||
// ctx->shuffle(dstWires);
|
||||
// }
|
||||
//
|
||||
// WireId src = srcWires[index];
|
||||
// WireId dst = dstWires[index++];
|
||||
// std::unordered_map<WireId, PipId> route;
|
||||
//
|
||||
//#if NUM_FUZZ_ROUTES <= 1000
|
||||
// if (!ctx->getActualRouteDelay(src, dst, nullptr, &route, false))
|
||||
// continue;
|
||||
//#else
|
||||
// if (!ctx->getActualRouteDelay(src, dst, nullptr, &route, true))
|
||||
// continue;
|
||||
//#endif
|
||||
//
|
||||
// WireId cursor = dst;
|
||||
// delay_t delay = 0;
|
||||
//
|
||||
// while (1) {
|
||||
// delay += ctx->getWireDelay(cursor).maxDelay();
|
||||
//
|
||||
// printf("%s %d %d %s %s %d %d\n", cursor == dst ? "dst" : "src",
|
||||
// int(ctx->chip_info->wire_data[cursor.index].x), int(ctx->chip_info->wire_data[cursor.index].y),
|
||||
// ctx->getWireType(cursor).c_str(ctx), ctx->getWireName(cursor).c_str(ctx), int(delay),
|
||||
// int(ctx->estimateDelay(cursor, dst)));
|
||||
//
|
||||
// if (cursor == src)
|
||||
// break;
|
||||
//
|
||||
// PipId pip = route.at(cursor);
|
||||
// delay += ctx->getPipDelay(pip).maxDelay();
|
||||
// cursor = ctx->getPipSrcWire(pip);
|
||||
// }
|
||||
//
|
||||
// cnt++;
|
||||
//
|
||||
// if (cnt % 100 == 0)
|
||||
// fprintf(stderr, "Fuzzed %d arcs.\n", cnt);
|
||||
// }
|
||||
}
|
||||
|
||||
delay_t Arch::estimateDelay(WireId src, WireId dst) const
|
||||
|
42
xc7/pack.cc
42
xc7/pack.cc
@ -336,16 +336,16 @@ static void pack_constants(Context *ctx)
|
||||
std::unique_ptr<NetInfo> gnd_net = std::unique_ptr<NetInfo>(new NetInfo);
|
||||
gnd_net->name = ctx->id("$PACKER_GND_NET");
|
||||
gnd_net->driver.cell = gnd_cell.get();
|
||||
gnd_net->driver.port = ctx->id("O");
|
||||
gnd_cell->ports.at(ctx->id("O")).net = gnd_net.get();
|
||||
gnd_net->driver.port = ctx->id("A");
|
||||
gnd_cell->ports.at(ctx->id("A")).net = gnd_net.get();
|
||||
|
||||
std::unique_ptr<CellInfo> vcc_cell = create_ice_cell(ctx, ctx->id("XC7_LC"), "$PACKER_VCC");
|
||||
vcc_cell->params[ctx->id("LUT_INIT")] = "1";
|
||||
std::unique_ptr<NetInfo> vcc_net = std::unique_ptr<NetInfo>(new NetInfo);
|
||||
vcc_net->name = ctx->id("$PACKER_VCC_NET");
|
||||
vcc_net->driver.cell = vcc_cell.get();
|
||||
vcc_net->driver.port = ctx->id("O");
|
||||
vcc_cell->ports.at(ctx->id("O")).net = vcc_net.get();
|
||||
vcc_net->driver.port = ctx->id("A");
|
||||
vcc_cell->ports.at(ctx->id("A")).net = vcc_net.get();
|
||||
|
||||
std::vector<IdString> dead_nets;
|
||||
|
||||
@ -451,6 +451,7 @@ static bool is_logic_port(BaseCtx *ctx, const PortRef &port)
|
||||
|
||||
static void insert_global(Context *ctx, NetInfo *net, bool is_reset, bool is_cen, bool is_logic)
|
||||
{
|
||||
asm("int3");
|
||||
std::string glb_name = net->name.str(ctx) + std::string("_$glb_") + (is_reset ? "sr" : (is_cen ? "ce" : "clk"));
|
||||
std::unique_ptr<CellInfo> gb = create_ice_cell(ctx, id_BUFGCTRL, "$bufg_" + glb_name);
|
||||
gb->ports[ctx->id("I0")].net = net;
|
||||
@ -847,25 +848,25 @@ static void pack_special(Context *ctx)
|
||||
|
||||
// Find wire that will be driven by this port.
|
||||
const auto pll_out_wire = ctx->getBelPinWire(pll_bel, port.name);
|
||||
NPNR_ASSERT(pll_out_wire.index != -1);
|
||||
NPNR_ASSERT(pll_out_wire != WireId());
|
||||
|
||||
// Now, constrain all LUTs on the output of the signal to be at
|
||||
// the correct Bel relative to the PLL Bel.
|
||||
int x = ctx->chip_info->wire_data[pll_out_wire.index].x;
|
||||
int y = ctx->chip_info->wire_data[pll_out_wire.index].y;
|
||||
int z = 0;
|
||||
for (const auto &user : port.net->users) {
|
||||
NPNR_ASSERT(user.cell != nullptr);
|
||||
NPNR_ASSERT(user.cell->type == ctx->id("XC7_LC"));
|
||||
//int x = ctx->chip_info->wire_data[pll_out_wire.index].x;
|
||||
//int y = ctx->chip_info->wire_data[pll_out_wire.index].y;
|
||||
//int z = 0;
|
||||
//for (const auto &user : port.net->users) {
|
||||
// NPNR_ASSERT(user.cell != nullptr);
|
||||
// NPNR_ASSERT(user.cell->type == ctx->id("XC7_LC"));
|
||||
|
||||
// TODO(q3k): handle when the Bel might be already the
|
||||
// target of another constraint.
|
||||
NPNR_ASSERT(z < 8);
|
||||
auto target_bel = ctx->getBelByLocation(Loc(x, y, z++));
|
||||
auto target_bel_name = ctx->getBelName(target_bel).str(ctx);
|
||||
user.cell->attrs[ctx->id("BEL")] = target_bel_name;
|
||||
log_info(" constrained '%s' to %s\n", user.cell->name.c_str(ctx), target_bel_name.c_str());
|
||||
}
|
||||
// // TODO(q3k): handle when the Bel might be already the
|
||||
// // target of another constraint.
|
||||
// NPNR_ASSERT(z < 8);
|
||||
// auto target_bel = ctx->getBelByLocation(Loc(x, y, z++));
|
||||
// auto target_bel_name = ctx->getBelName(target_bel).str(ctx);
|
||||
// user.cell->attrs[ctx->id("BEL")] = target_bel_name;
|
||||
// log_info(" constrained '%s' to %s\n", user.cell->name.c_str(ctx), target_bel_name.c_str());
|
||||
//}
|
||||
}
|
||||
|
||||
new_cells.push_back(std::move(packed));
|
||||
@ -887,7 +888,8 @@ bool Arch::pack()
|
||||
try {
|
||||
log_break();
|
||||
pack_constants(ctx);
|
||||
promote_globals(ctx);
|
||||
// TODO
|
||||
//promote_globals(ctx);
|
||||
pack_io(ctx);
|
||||
pack_lut_lutffs(ctx);
|
||||
pack_nonlut_ffs(ctx);
|
||||
|
Loading…
Reference in New Issue
Block a user