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loop wire range

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This commit is contained in:
Miodrag Milanovic 2024-11-21 14:33:07 +01:00
parent 5c46ab5f7e
commit 57d098f952
1 changed files with 9 additions and 7 deletions
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4
himbaechel/arch.cc
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@ -509,13 +509,15 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE; GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
uarch->drawBel(ret, style, getBelType(bel), getBelLocation(bel)); uarch->drawBel(ret, style, getBelType(bel), getBelLocation(bel));
} else if (decal.type == DecalId::TYPE_WIRE) { } else if (decal.type == DecalId::TYPE_WIRE) {
WireId wire(decal.tile, decal.index); WireId w(decal.tile, decal.index);
for (WireId wire: get_tile_wire_range(w)) {
auto wire_type = getWireType(wire); auto wire_type = getWireType(wire);
GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE; GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
Loc loc; Loc loc;
tile_xy(chip_info, wire.tile, loc.x, loc.y); tile_xy(chip_info, wire.tile, loc.x, loc.y);
int32_t tilewire = chip_wire_info(chip_info, wire).tile_wire; int32_t tilewire = chip_wire_info(chip_info, wire).tile_wire;
uarch->drawWire(ret, style, loc, wire_type, tilewire, get_tile_type(wire.tile)); uarch->drawWire(ret, style, loc, wire_type, tilewire, get_tile_type(wire.tile));
}
} else if (decal.type == DecalId::TYPE_PIP) { } else if (decal.type == DecalId::TYPE_PIP) {
PipId pip(decal.tile, decal.index); PipId pip(decal.tile, decal.index);
WireId src_wire = getPipSrcWire(pip); WireId src_wire = getPipSrcWire(pip);