display freq with two digits after decimal point
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parent
909917cb61
commit
582cd526ac
@ -1308,13 +1308,13 @@ class MachXO2Packer
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if (to->clkconstr != nullptr) {
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if (!equals_epsilon_constr(*to->clkconstr, *constr) && user_constrained.count(to->name))
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log_warning(
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" Overriding derived constraint of %.1f MHz on net %s with user-specified constraint of "
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"%.1f MHz.\n",
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" Overriding derived constraint of %.2f MHz on net %s with user-specified constraint of "
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"%.2f MHz.\n",
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MHz(to->clkconstr->period.min_delay), to->name.c_str(ctx), MHz(constr->period.min_delay));
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return;
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}
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to->clkconstr = std::move(constr);
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log_info(" Derived frequency constraint of %.1f MHz for net %s\n", MHz(to->clkconstr->period.minDelay()),
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log_info(" Derived frequency constraint of %.2f MHz for net %s\n", MHz(to->clkconstr->period.minDelay()),
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to->name.c_str(ctx));
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changed_nets.insert(to->name);
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};
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@ -1330,8 +1330,8 @@ class MachXO2Packer
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delay_t(from->clkconstr->period.minDelay() / ratio)) &&
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user_constrained.count(to->name))
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log_warning(
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" Overriding derived constraint of %.1f MHz on net %s with user-specified constraint of "
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"%.1f MHz.\n",
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" Overriding derived constraint of %.2f MHz on net %s with user-specified constraint of "
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"%.2f MHz.\n",
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MHz(to->clkconstr->period.minDelay()), to->name.c_str(ctx),
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MHz(delay_t(from->clkconstr->period.minDelay() / ratio)));
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return;
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@ -1343,7 +1343,7 @@ class MachXO2Packer
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DelayPair(ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->high.min_delay) / ratio));
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to->clkconstr->period =
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DelayPair(ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->period.min_delay) / ratio));
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log_info(" Derived frequency constraint of %.1f MHz for net %s\n", MHz(to->clkconstr->period.minDelay()),
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log_info(" Derived frequency constraint of %.2f MHz for net %s\n", MHz(to->clkconstr->period.minDelay()),
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to->name.c_str(ctx));
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changed_nets.insert(to->name);
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};
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@ -1389,7 +1389,7 @@ class MachXO2Packer
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delay_t period_in;
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if (!get_period(ci, id_CLKI, period_in))
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continue;
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log_info(" Input frequency of PLL '%s' is constrained to %.1f MHz\n", ci->name.c_str(ctx),
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log_info(" Input frequency of PLL '%s' is constrained to %.2f MHz\n", ci->name.c_str(ctx),
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MHz(period_in));
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double period_in_div = period_in * int_or_default(ci->params, id_CLKI_DIV, 1);
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std::string path = str_or_default(ci->params, id_FEEDBK_PATH, "CLKOP");
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@ -1410,7 +1410,7 @@ class MachXO2Packer
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double vco_period = period_in_div / feedback_div;
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double vco_freq = MHz(vco_period);
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if (vco_freq < 400 || vco_freq > 800)
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log_info(" Derived VCO frequency %.1f MHz of PLL '%s' is out of legal range [400MHz, "
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log_info(" Derived VCO frequency %.2f MHz of PLL '%s' is out of legal range [400MHz, "
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"800MHz]\n",
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vco_freq, ci->name.c_str(ctx));
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set_constraint(ci, id_CLKOP,
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