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nexus: Fix LRAM pin types

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2020-12-07 13:26:45 +00:00
parent f923d32620
commit 588042dc99
2 changed files with 11 additions and 10 deletions
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17
nexus/arch.h
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@ -838,14 +838,15 @@ enum CellPinStyle
PINBIT_1 = 0x2000, // pin has an explicit bit that must be set if tied to 1
PINBIT_CIBMUX = 0x4000, // pin's CIBMUX must be floating for pin to be 1
PINSTYLE_NONE = 0x0000, // default
PINSTYLE_CIB = 0x4012, // 'CIB' signal, floats high but explicitly zeroed if not used
PINSTYLE_CLK = 0x0107, // CLK type signal, invertible and defaults to disconnected
PINSTYLE_CE = 0x0027, // CE type signal, invertible and defaults to enabled
PINSTYLE_LSR = 0x0017, // LSR type signal, invertible and defaults to not reset
PINSTYLE_DEDI = 0x0000, // dedicated signals, leave alone
PINSTYLE_PU = 0x4022, // signals that float high and default high
PINSTYLE_T = 0x4027, // PIO 'T' signal
PINSTYLE_NONE = 0x0000, // default
PINSTYLE_CIB = 0x4012, // 'CIB' signal, floats high but explicitly zeroed if not used
PINSTYLE_CLK = 0x0107, // CLK type signal, invertible and defaults to disconnected
PINSTYLE_CE = 0x0027, // CE type signal, invertible and defaults to enabled
PINSTYLE_LSR = 0x0017, // LSR type signal, invertible and defaults to not reset
PINSTYLE_DEDI = 0x0000, // dedicated signals, leave alone
PINSTYLE_PU = 0x4022, // signals that float high and default high
PINSTYLE_PU_NONCIB = 0x0022, // signals that float high and default high
PINSTYLE_T = 0x4027, // PIO 'T' signal
PINSTYLE_ADLSB = 0x4017, // special case of the EBR address MSBs
PINSTYLE_INV_PD = 0x0017, // invertible, pull down by default

4
nexus/pins.cc
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@ -171,8 +171,8 @@ static const std::unordered_map<IdString, Arch::CellPinsData> base_cell_pin_data
{id_LRAM_CORE,
{
{id_CLK, PINSTYLE_CLK},
{id_CEA, PINSTYLE_CE},
{id_CEB, PINSTYLE_CE},
{id_CEA, PINSTYLE_PU_NONCIB},
{id_CEB, PINSTYLE_PU_NONCIB},
{id_OCEA, PINSTYLE_PU},
{id_OCEB, PINSTYLE_PU},
{id_CSA, PINSTYLE_PU},