Load timing data
This commit is contained in:
Miodrag Milanovic
myrtle
parent
e8602fb56d
commit
58cb8a830a
@ -47,6 +47,7 @@ void IdString::initialize_arch(const BaseCtx *ctx)
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// ---------------------------------------------------------------
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static void get_chip_info(std::string device, const ChipInfoPOD **chip_info, const PackageInfoPOD **package_info,
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const SpeedGradePOD **speed_grade,
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const char **device_name, const char **package_name)
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{
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std::stringstream ss(available_devices);
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@ -58,7 +59,7 @@ static void get_chip_info(std::string device, const ChipInfoPOD **chip_info, con
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continue; // chipdb not available
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for (auto &chip : db_ptr->get()->variants) {
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for (auto &pkg : chip.packages) {
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for (auto &speedgrade : chip.speed_grades) {
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for (auto &speedgrade : chip.speeds) {
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for (auto &rating : chip.suffixes) {
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std::string devname = stringf("%s-%d%s%s", chip.name.get(), speedgrade.speed,
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pkg.short_name.get(), rating.suffix.get());
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@ -67,6 +68,7 @@ static void get_chip_info(std::string device, const ChipInfoPOD **chip_info, con
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*package_info = nullptr;
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*package_name = pkg.name.get();
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*device_name = chip.name.get();
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*speed_grade = &(db_ptr->get()->speed_grades[speedgrade.index]);
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for (auto &pi : db_ptr->get()->package_info) {
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if (pkg.name.get() == pi.name.get()) {
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*package_info = π
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@ -86,7 +88,7 @@ static void get_chip_info(std::string device, const ChipInfoPOD **chip_info, con
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Arch::Arch(ArchArgs args) : args(args)
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{
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get_chip_info(args.device, &chip_info, &package_info, &device_name, &package_name);
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get_chip_info(args.device, &chip_info, &package_info, &speed_grade, &device_name, &package_name);
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if (chip_info == nullptr)
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log_error("Unsupported MachXO2 chip type.\n");
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if (chip_info->const_id_count != DB_CONST_ID_COUNT)
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@ -165,7 +167,7 @@ void Arch::list_devices()
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continue; // chipdb not available
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for (auto &chip : db_ptr->get()->variants) {
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for (auto &pkg : chip.packages) {
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for (auto &speedgrade : chip.speed_grades) {
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for (auto &speedgrade : chip.speeds) {
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for (auto &rating : chip.suffixes) {
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log(" %s-%d%s%s\n", chip.name.get(), speedgrade.speed, pkg.short_name.get(),
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rating.suffix.get());
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@ -58,10 +58,9 @@ NPNR_PACKED_STRUCT(struct BelPortPOD {
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NPNR_PACKED_STRUCT(struct PipInfoPOD {
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LocationPOD src, dst;
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int32_t src_idx, dst_idx;
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int32_t timing_class;
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int16_t tile_type;
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int16_t timing_class;
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int8_t tile_type;
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int8_t pip_type;
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int8_t padding;
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int16_t lutperm_flags;
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int16_t padding2;
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});
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@ -117,6 +116,40 @@ NPNR_PACKED_STRUCT(struct TileNamePOD {
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NPNR_PACKED_STRUCT(struct TileInfoPOD { RelSlice<TileNamePOD> tile_names; });
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NPNR_PACKED_STRUCT(struct CellPropDelayPOD {
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int32_t from_port;
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int32_t to_port;
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int32_t min_delay;
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int32_t max_delay;
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});
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NPNR_PACKED_STRUCT(struct CellSetupHoldPOD {
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int32_t sig_port;
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int32_t clock_port;
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int32_t min_setup;
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int32_t max_setup;
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int32_t min_hold;
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int32_t max_hold;
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});
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NPNR_PACKED_STRUCT(struct CellTimingPOD {
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int32_t cell_type;
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RelSlice<CellPropDelayPOD> prop_delays;
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RelSlice<CellSetupHoldPOD> setup_holds;
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});
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NPNR_PACKED_STRUCT(struct PipDelayPOD {
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int32_t min_base_delay;
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int32_t max_base_delay;
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int32_t min_fanout_adder;
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int32_t max_fanout_adder;
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});
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NPNR_PACKED_STRUCT(struct SpeedGradePOD {
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RelSlice<CellTimingPOD> cell_timings;
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RelSlice<PipDelayPOD> pip_classes;
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});
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NPNR_PACKED_STRUCT(struct PackageSupportedPOD {
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RelPtr<char> name;
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RelPtr<char> short_name;
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@ -124,12 +157,15 @@ NPNR_PACKED_STRUCT(struct PackageSupportedPOD {
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NPNR_PACKED_STRUCT(struct SuffixeSupportedPOD { RelPtr<char> suffix; });
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NPNR_PACKED_STRUCT(struct SpeedSupportedPOD { int32_t speed; });
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NPNR_PACKED_STRUCT(struct SpeedSupportedPOD {
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int16_t speed;
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int16_t index;
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});
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NPNR_PACKED_STRUCT(struct VariantInfoPOD {
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RelPtr<char> name;
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RelSlice<PackageSupportedPOD> packages;
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RelSlice<SpeedSupportedPOD> speed_grades;
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RelSlice<SpeedSupportedPOD> speeds;
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RelSlice<SuffixeSupportedPOD> suffixes;
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});
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@ -148,6 +184,7 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD {
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RelSlice<TileInfoPOD> tile_info;
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RelSlice<VariantInfoPOD> variants;
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RelSlice<SpineInfoPOD> spines;
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RelSlice<SpeedGradePOD> speed_grades;
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});
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/************************ End of chipdb section. ************************/
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@ -383,6 +420,8 @@ struct Arch : BaseArch<ArchRanges>
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{
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const ChipInfoPOD *chip_info;
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const PackageInfoPOD *package_info;
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const SpeedGradePOD *speed_grade;
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const char *package_name;
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const char *device_name;
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@ -1,3 +1,29 @@
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X(DP8KC_REGMODE_A_NOREG_REGMODE_B_NOREG)
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X(DP8KC_REGMODE_A_NOREG_REGMODE_B_OUTREG)
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X(DP8KC_REGMODE_A_OUTREG_REGMODE_B_NOREG)
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X(DP8KC_REGMODE_A_OUTREG_REGMODE_B_OUTREG)
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X(DP8KC_WRITEMODE_A_NORMAL_WRITEMODE_B_NORMAL)
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X(DP8KC_WRITEMODE_A_NORMAL_WRITEMODE_B_READBEFOREWRITE)
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X(DP8KC_WRITEMODE_A_NORMAL_WRITEMODE_B_WRITETHROUGH)
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X(PIO_IOTYPE_LVCMOS12)
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X(PIO_IOTYPE_LVCMOS15)
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X(PIO_IOTYPE_LVCMOS18)
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X(PIO_IOTYPE_LVCMOS25)
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X(PIO_IOTYPE_LVCMOS33)
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X(PIO_IOTYPE_LVDS)
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X(PIO_IOTYPE_SSTL15_I)
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X(PIO_IOTYPE_SSTL15_II)
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X(PIO_IOTYPE_SSTL18_I)
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X(PIO_IOTYPE_SSTL18_II)
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X(PIO_IOTYPE_LVDS25)
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X(PIO_IOTYPE_LVPECL33)
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X(PIO_IOTYPE_LVTTL33)
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X(PIO_IOTYPE_MIPI)
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X(PAD)
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X(PADDI)
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X(PADDO)
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X(PADDT)
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X(TRELLIS_SLICE)
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X(A0)
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X(B0)
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@ -612,7 +638,6 @@ X(TIOLOGIC)
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X(TSIOLOGIC)
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X(RIOLOGIC)
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X(PADDI)
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X(INDD)
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X(TDX0)
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X(TDX1)
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@ -666,3 +691,6 @@ X(TAMPERDETCLK)
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X(RESEN)
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X(PULLUPEN)
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X(SLEWRATE)
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X(TRELLIS_COMB_CARRY0)
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X(TRELLIS_COMB_CARRY1)
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@ -18,6 +18,8 @@ args = parser.parse_args()
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sys.path += args.libdir
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import pytrellis
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import database
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import pip_classes
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import timing_dbs
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with open(args.gfxh) as f:
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state = 0
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@ -213,7 +215,158 @@ def process_pio_db(rg, device):
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if bel_idx is not None:
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pindata.append((loc, bel_idx, bank, pinfunc, dqs))
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def write_database(dev_name, chip, rg, endianness):
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speed_grade_names = {
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"MachXO2": ["1", "2", "3", "4", "5", "6"],
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"MachXO3": ["5", "6"],
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"MachXO3D": ["2", "3", "5", "6"]
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}
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speed_grade_cells = {}
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speed_grade_pips = {}
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pip_class_to_idx = {"default": 0, "zero": 1}
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timing_port_xform = {
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"RAD0": "D0",
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"RAD1": "B0",
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"RAD2": "C0",
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"RAD3": "A0",
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}
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delay_db = {}
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# Convert from Lattice-style grouped SLICE to new nextpnr split style SLICE
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def postprocess_timing_data(cells):
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def delay_diff(x, y):
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return (x[0] - y[0], x[1] - y[1])
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split_cells = {}
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comb_delays = {}
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comb_delays[("A", "F")] = delay_db["SLICE"][("A0", "F0")]
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comb_delays[("B", "F")] = delay_db["SLICE"][("B0", "F0")]
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comb_delays[("C", "F")] = delay_db["SLICE"][("C0", "F0")]
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comb_delays[("D", "F")] = delay_db["SLICE"][("D0", "F0")]
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#comb_delays[("A", "OFX")] = delay_db["SLICE"][("A0", "OFX0")]
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#comb_delays[("B", "OFX")] = delay_db["SLICE"][("B0", "OFX0")]
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#comb_delays[("C", "OFX")] = delay_db["SLICE"][("C0", "OFX0")]
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#comb_delays[("D", "OFX")] = delay_db["SLICE"][("D0", "OFX0")]
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#comb_delays[("M", "OFX")] = delay_db["SLICE"][("M0", "OFX0")] # worst case
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#comb_delays[("F1", "OFX")] = delay_diff(delay_db["SLICE"][("A1", "OFX0")],
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# delay_db["SLICE"][("A1", "F1")])
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#comb_delays[("FXA", "OFX")] = delay_db["SLICE"][("FXA", "OFX1")]
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#comb_delays[("FXB", "OFX")] = delay_db["SLICE"][("FXB", "OFX1")]
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split_cells["TRELLIS_COMB"] = comb_delays
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carry0_delays = {}
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carry0_delays[("A", "F")] = delay_db["SLICE"][("A0", "F0")]
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carry0_delays[("B", "F")] = delay_db["SLICE"][("B0", "F0")]
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carry0_delays[("C", "F")] = delay_db["SLICE"][("C0", "F0")]
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carry0_delays[("D", "F")] = delay_db["SLICE"][("D0", "F0")]
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#carry0_delays[("A", "FCO")] = delay_db["SLICE"][("A0", "FCO")]
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#carry0_delays[("B", "FCO")] = delay_db["SLICE"][("B0", "FCO")]
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#carry0_delays[("C", "FCO")] = delay_db["SLICE"][("C0", "FCO")]
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#carry0_delays[("D", "FCO")] = delay_db["SLICE"][("D0", "FCO")]
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#carry0_delays[("FCI", "F")] = delay_db["SLICE"][("FCI", "F0")]
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#carry0_delays[("FCI", "FCO")] = delay_db["SLICE"][("FCI", "FCO")]
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split_cells["TRELLIS_COMB_CARRY0"] = carry0_delays
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carry1_delays = {}
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carry1_delays[("A", "F")] = delay_db["SLICE"][("A1", "F1")]
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carry1_delays[("B", "F")] = delay_db["SLICE"][("B1", "F1")]
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carry1_delays[("C", "F")] = delay_db["SLICE"][("C1", "F1")]
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carry1_delays[("D", "F")] = delay_db["SLICE"][("D1", "F1")]
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#carry1_delays[("A", "FCO")] = delay_db["SLICE"][("A1", "FCO")]
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#carry1_delays[("B", "FCO")] = delay_db["SLICE"][("B1", "FCO")]
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#carry1_delays[("C", "FCO")] = delay_db["SLICE"][("C1", "FCO")]
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#carry1_delays[("D", "FCO")] = delay_db["SLICE"][("D1", "FCO")]
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#carry1_delays[("FCI", "F")] = delay_diff(delay_db["SLICE"][("FCI", "F1")], delay_db["SLICE"][("FCI", "FCO")])
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#carry1_delays[("FCI", "FCO")] = (0, 0)
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split_cells["TRELLIS_COMB_CARRY1"] = carry1_delays
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for celltype, celldelays in sorted(split_cells.items()):
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delays = []
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setupholds = []
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for (from_pin, to_pin), (min_delay, max_delay) in sorted(celldelays.items()):
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delays.append((constids[from_pin], constids[to_pin], min_delay, max_delay))
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cells.append((constids[celltype], delays, setupholds))
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def process_timing_data(family):
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for grade in speed_grade_names[family]:
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with open(timing_dbs.cells_db_path(family, grade)) as f:
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cell_data = json.load(f)
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cells = []
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for cell, cdata in sorted(cell_data.items()):
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celltype = constids[cell.replace(":", "_").replace("=", "_").replace(",", "_")]
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delays = []
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setupholds = []
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delay_db[cell] = {}
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for entry in cdata:
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if entry["type"] == "Width":
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continue
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elif entry["type"] == "IOPath":
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from_pin = entry["from_pin"][1] if type(entry["from_pin"]) is list else entry["from_pin"]
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if from_pin in timing_port_xform:
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from_pin = timing_port_xform[from_pin]
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to_pin = entry["to_pin"]
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if to_pin in timing_port_xform:
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to_pin = timing_port_xform[to_pin]
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min_delay = min(entry["rising"][0], entry["falling"][0])
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max_delay = min(entry["rising"][2], entry["falling"][2])
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delay_db[cell][(from_pin, to_pin)] = (min_delay, max_delay)
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delays.append((constids[from_pin], constids[to_pin], min_delay, max_delay))
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elif entry["type"] == "SetupHold":
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if type(entry["pin"]) is list:
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continue
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pin = constids[entry["pin"]]
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clock = constids[entry["clock"][1]]
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min_setup = entry["setup"][0]
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max_setup = entry["setup"][2]
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min_hold = entry["hold"][0]
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max_hold = entry["hold"][2]
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setupholds.append((pin, clock, min_setup, max_setup, min_hold, max_hold))
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else:
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assert False, entry["type"]
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cells.append((celltype, delays, setupholds))
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postprocess_timing_data(cells)
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pip_class_delays = []
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for i in range(len(pip_class_to_idx)):
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pip_class_delays.append((50, 50, 0, 0))
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pip_class_delays[pip_class_to_idx["zero"]] = (0, 0, 0, 0)
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with open(timing_dbs.interconnect_db_path(family, grade)) as f:
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interconn_data = json.load(f)
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for pipclass, pipdata in sorted(interconn_data.items()):
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min_delay = pipdata["delay"][0] * 1.1
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max_delay = pipdata["delay"][2] * 1.1
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min_fanout = pipdata["fanout"][0]
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max_fanout = pipdata["fanout"][2]
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if grade == "6":
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pip_class_to_idx[pipclass] = len(pip_class_delays)
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pip_class_delays.append((min_delay, max_delay, min_fanout, max_fanout))
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else:
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if pipclass in pip_class_to_idx:
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pip_class_delays[pip_class_to_idx[pipclass]] = (min_delay, max_delay, min_fanout, max_fanout)
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speed_grade_cells[grade] = cells
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speed_grade_pips[grade] = pip_class_delays
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def get_pip_class(wire_from, wire_to):
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if "FCO" in wire_from or "FCI" in wire_to:
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return pip_class_to_idx["zero"]
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if "F5" in wire_from or "FX" in wire_from or "FXA" in wire_to or "FXB" in wire_to:
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return pip_class_to_idx["zero"]
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class_name = pip_classes.get_pip_class(wire_from, wire_to)
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if class_name is None or class_name not in pip_class_to_idx:
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class_name = "default"
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return pip_class_to_idx[class_name]
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def write_database(family, dev_name, chip, rg, endianness):
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def write_loc(loc, sym_name):
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bba.u16(loc.x, "%s.x" % sym_name)
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bba.u16(loc.y, "%s.y" % sym_name)
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@ -261,13 +414,10 @@ def write_database(dev_name, chip, rg, endianness):
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bba.u32(arc.sinkWire.id, "dst_idx {}".format(get_wire_name(arc.sinkWire.rel, arc.sinkWire.id)))
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src_name = get_wire_name(arc.srcWire.rel, arc.srcWire.id)
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snk_name = get_wire_name(arc.sinkWire.rel, arc.sinkWire.id)
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# TODO: ECP5 timing-model-specific. Reuse for MachXO2?
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# bba.u32(get_pip_class(src_name, snk_name), "timing_class")
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bba.u32(0, "timing_class")
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bba.u16(get_tiletype_index(rg.to_str(arc.tiletype)), "tile_type")
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bba.u16(get_pip_class(src_name, snk_name), "timing_class")
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bba.u8(get_tiletype_index(rg.to_str(arc.tiletype)), "tile_type")
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cls = arc.cls
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bba.u8(arc.cls, "pip_type")
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bba.u8(0, "padding")
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bba.u8(cls, "pip_type")
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bba.u16(arc.lutperm_flags, "lutperm_flags")
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bba.u16(0, "padding2")
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@ -375,6 +525,45 @@ def write_database(dev_name, chip, rg, endianness):
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for tt, idx in sorted(tiletype_names.items(), key=lambda x: x[1]):
|
||||
bba.s(tt, "name")
|
||||
|
||||
for grade in speed_grade_names[family]:
|
||||
for cell in speed_grade_cells[grade]:
|
||||
celltype, delays, setupholds = cell
|
||||
if len(delays) > 0:
|
||||
bba.l("cell_%d_delays_%s" % (celltype, grade))
|
||||
for delay in delays:
|
||||
from_pin, to_pin, min_delay, max_delay = delay
|
||||
bba.u32(from_pin, "from_pin")
|
||||
bba.u32(to_pin, "to_pin")
|
||||
bba.u32(min_delay, "min_delay")
|
||||
bba.u32(max_delay, "max_delay")
|
||||
if len(setupholds) > 0:
|
||||
bba.l("cell_%d_setupholds_%s" % (celltype, grade))
|
||||
for sh in setupholds:
|
||||
pin, clock, min_setup, max_setup, min_hold, max_hold = sh
|
||||
bba.u32(pin, "sig_port")
|
||||
bba.u32(clock, "clock_port")
|
||||
bba.u32(min_setup, "min_setup")
|
||||
bba.u32(max_setup, "max_setup")
|
||||
bba.u32(min_hold, "min_hold")
|
||||
bba.u32(max_hold, "max_hold")
|
||||
bba.l("cell_timing_data_%s" % grade)
|
||||
for cell in speed_grade_cells[grade]:
|
||||
celltype, delays, setupholds = cell
|
||||
bba.u32(celltype, "cell_type")
|
||||
bba.r_slice("cell_%d_delays_%s" % (celltype, grade) if len(delays) > 0 else None, len(delays), "delays")
|
||||
bba.r_slice("cell_%d_setupholds_%s" % (celltype, grade) if len(delays) > 0 else None, len(setupholds), "setupholds")
|
||||
bba.l("pip_timing_data_%s" % grade)
|
||||
for pipclass in speed_grade_pips[grade]:
|
||||
min_delay, max_delay, min_fanout, max_fanout = pipclass
|
||||
bba.u32(min_delay, "min_delay")
|
||||
bba.u32(max_delay, "max_delay")
|
||||
bba.u32(min_fanout, "min_fanout")
|
||||
bba.u32(max_fanout, "max_fanout")
|
||||
bba.l("speed_grade_data")
|
||||
for grade in speed_grade_names[family]:
|
||||
bba.r_slice("cell_timing_data_%s" % grade, len(speed_grade_cells[grade]), "cell_timings")
|
||||
bba.r_slice("pip_timing_data_%s" % grade, len(speed_grade_pips[grade]), "pip_classes")
|
||||
|
||||
for name, var_data in sorted(variants.items()):
|
||||
bba.l("supported_packages_%s" % name, "PackageSupportedPOD")
|
||||
for package in var_data["packages"]:
|
||||
@ -382,7 +571,8 @@ def write_database(dev_name, chip, rg, endianness):
|
||||
bba.s(package_shortname(package, chip.info.family), "short_name")
|
||||
bba.l("supported_speed_grades_%s" % name, "SpeedSupportedPOD")
|
||||
for speed in var_data["speeds"]:
|
||||
bba.u32(speed, "speed")
|
||||
bba.u16(speed, "speed")
|
||||
bba.u16(speed_grade_names[family].index(str(speed)), "index")
|
||||
bba.l("supported_suffixes_%s" % name, "SuffixeSupportedPOD")
|
||||
for suffix in var_data["suffixes"]:
|
||||
bba.s(suffix, "suffix")
|
||||
@ -414,6 +604,7 @@ def write_database(dev_name, chip, rg, endianness):
|
||||
bba.r_slice("tiles_info", (max_col + 1) * (max_row + 1), "tile_info")
|
||||
bba.r_slice("variant_data", len(variants), "variant_info")
|
||||
bba.r_slice("spine_info", len(spines), "spine_info")
|
||||
bba.r_slice("speed_grade_data", len(speed_grade_names[family]), "speed_grades")
|
||||
|
||||
bba.pop()
|
||||
return bba
|
||||
@ -492,9 +683,10 @@ def main():
|
||||
rg = pytrellis.make_optimized_chipdb(chip, include_lutperm_pips=True, split_slice_mode=True)
|
||||
max_row = chip.get_max_row()
|
||||
max_col = chip.get_max_col()
|
||||
process_timing_data(dev_family[args.device])
|
||||
process_pio_db(rg, args.device)
|
||||
process_devices_db(chip.info.family, chip.info.name)
|
||||
bba = write_database(args.device, chip, rg, "le")
|
||||
bba = write_database(dev_family[args.device],args.device, chip, rg, "le")
|
||||
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user