Merge pull request #158 from YosysHQ/improve_error
Error reporting improvements
This commit is contained in:
commit
58e9c6f32e
@ -9,7 +9,7 @@ bool check_all_nets_driven(Context *ctx)
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{
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{
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const bool debug = false;
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const bool debug = false;
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log_info("Rule checker, Verifying pre-placed design\n");
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log_info("Rule checker, verifying imported design\n");
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for (auto &cell_entry : ctx->cells) {
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for (auto &cell_entry : ctx->cells) {
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CellInfo *cell = cell_entry.second.get();
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CellInfo *cell = cell_entry.second.get();
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@ -670,7 +670,8 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
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}
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}
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return TMG_IGNORE;
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return TMG_IGNORE;
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} else {
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} else {
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NPNR_ASSERT_FALSE_STR("no timing data for cell type '" + cell->type.str(this) + "'");
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log_error("cell type '%s' is unsupported (instantiated as '%s')\n", cell->type.c_str(this),
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cell->name.c_str(this));
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}
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}
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}
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}
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@ -951,7 +951,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
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return TMG_IGNORE;
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return TMG_IGNORE;
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return TMG_ENDPOINT;
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return TMG_ENDPOINT;
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}
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}
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log_error("no timing info for port '%s' of cell type '%s'\n", port.c_str(this), cell->type.c_str(this));
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log_error("cell type '%s' is unsupported (instantiated as '%s')\n", cell->type.c_str(this), cell->name.c_str(this));
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}
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}
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TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port, int index) const
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TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port, int index) const
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@ -478,6 +478,9 @@ static void pack_io(Context *ctx)
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}
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}
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packed_cells.insert(ci->name);
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packed_cells.insert(ci->name);
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std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(sb->attrs, sb->attrs.begin()));
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std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(sb->attrs, sb->attrs.begin()));
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if (!sb->attrs.count(ctx->id("BEL")))
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log_warning("IO '%s' is not constrained to a pin and will be automatically placed\n",
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ci->name.c_str(ctx));
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} else if (is_sb_io(ctx, ci) || is_sb_gb_io(ctx, ci)) {
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} else if (is_sb_io(ctx, ci) || is_sb_gb_io(ctx, ci)) {
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NetInfo *net = ci->ports.at(ctx->id("PACKAGE_PIN")).net;
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NetInfo *net = ci->ports.at(ctx->id("PACKAGE_PIN")).net;
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if ((net != nullptr) && (net->users.size() > 1))
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if ((net != nullptr) && (net->users.size() > 1))
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@ -520,12 +523,8 @@ static bool is_logic_port(BaseCtx *ctx, const PortRef &port)
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static void insert_global(Context *ctx, NetInfo *net, bool is_reset, bool is_cen, bool is_logic, int fanout)
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static void insert_global(Context *ctx, NetInfo *net, bool is_reset, bool is_cen, bool is_logic, int fanout)
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{
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{
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log_info("promoting %s%s%s%s (fanout %d)\n",
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log_info("promoting %s%s%s%s (fanout %d)\n", net->name.c_str(ctx), is_reset ? " [reset]" : "",
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net->name.c_str(ctx),
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is_cen ? " [cen]" : "", is_logic ? " [logic]" : "", fanout);
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is_reset ? " [reset]" : "",
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is_cen ? " [cen]" : "",
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is_logic ? " [logic]" : "",
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fanout);
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std::string glb_name = net->name.str(ctx) + std::string("_$glb_") + (is_reset ? "sr" : (is_cen ? "ce" : "clk"));
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std::string glb_name = net->name.str(ctx) + std::string("_$glb_") + (is_reset ? "sr" : (is_cen ? "ce" : "clk"));
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std::unique_ptr<CellInfo> gb = create_ice_cell(ctx, ctx->id("SB_GB"), "$gbuf_" + glb_name);
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std::unique_ptr<CellInfo> gb = create_ice_cell(ctx, ctx->id("SB_GB"), "$gbuf_" + glb_name);
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@ -594,7 +594,11 @@ void json_import_cell(Context *ctx, string modname, const std::vector<IdString>
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if (type == PORT_IN || type == PORT_INOUT) {
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if (type == PORT_IN || type == PORT_INOUT) {
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net->users.push_back(pr);
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net->users.push_back(pr);
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} else if (type == PORT_OUT) {
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} else if (type == PORT_OUT) {
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assert(net->driver.cell == nullptr);
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if (net->driver.cell != nullptr)
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log_error("multiple drivers on net '%s' (%s.%s and %s.%s)\n",
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net->name.c_str(ctx), net->driver.cell->name.c_str(ctx),
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net->driver.port.c_str(ctx), pr.cell->name.c_str(ctx),
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pr.port.c_str(ctx));
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net->driver = pr;
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net->driver = pr;
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}
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}
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}
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}
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