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Merge pull request #158 from YosysHQ/improve_error

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Error reporting improvements
This commit is contained in:
David Shah 2018-11-29 19:46:05 +00:00 committed by GitHub
commit 58e9c6f32e
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GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 14 additions and 10 deletions
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2
common/rulecheck.cc
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@ -9,7 +9,7 @@ bool check_all_nets_driven(Context *ctx)
{ {
const bool debug = false; const bool debug = false;
log_info("Rule checker, Verifying pre-placed design\n"); log_info("Rule checker, verifying imported design\n");
for (auto &cell_entry : ctx->cells) { for (auto &cell_entry : ctx->cells) {
CellInfo *cell = cell_entry.second.get(); CellInfo *cell = cell_entry.second.get();

3
ecp5/arch.cc
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@ -670,7 +670,8 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
} }
return TMG_IGNORE; return TMG_IGNORE;
} else { } else {
NPNR_ASSERT_FALSE_STR("no timing data for cell type '" + cell->type.str(this) + "'"); log_error("cell type '%s' is unsupported (instantiated as '%s')\n", cell->type.c_str(this),
cell->name.c_str(this));
} }
} }

2
ice40/arch.cc
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@ -951,7 +951,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
return TMG_IGNORE; return TMG_IGNORE;
return TMG_ENDPOINT; return TMG_ENDPOINT;
} }
log_error("no timing info for port '%s' of cell type '%s'\n", port.c_str(this), cell->type.c_str(this)); log_error("cell type '%s' is unsupported (instantiated as '%s')\n", cell->type.c_str(this), cell->name.c_str(this));
} }
TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port, int index) const TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port, int index) const

11
ice40/pack.cc
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@ -478,6 +478,9 @@ static void pack_io(Context *ctx)
} }
packed_cells.insert(ci->name); packed_cells.insert(ci->name);
std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(sb->attrs, sb->attrs.begin())); std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(sb->attrs, sb->attrs.begin()));
if (!sb->attrs.count(ctx->id("BEL")))
log_warning("IO '%s' is not constrained to a pin and will be automatically placed\n",
ci->name.c_str(ctx));
} else if (is_sb_io(ctx, ci) || is_sb_gb_io(ctx, ci)) { } else if (is_sb_io(ctx, ci) || is_sb_gb_io(ctx, ci)) {
NetInfo *net = ci->ports.at(ctx->id("PACKAGE_PIN")).net; NetInfo *net = ci->ports.at(ctx->id("PACKAGE_PIN")).net;
if ((net != nullptr) && (net->users.size() > 1)) if ((net != nullptr) && (net->users.size() > 1))
@ -520,12 +523,8 @@ static bool is_logic_port(BaseCtx *ctx, const PortRef &port)
static void insert_global(Context *ctx, NetInfo *net, bool is_reset, bool is_cen, bool is_logic, int fanout) static void insert_global(Context *ctx, NetInfo *net, bool is_reset, bool is_cen, bool is_logic, int fanout)
{ {
log_info("promoting %s%s%s%s (fanout %d)\n", log_info("promoting %s%s%s%s (fanout %d)\n", net->name.c_str(ctx), is_reset ? " [reset]" : "",
net->name.c_str(ctx), is_cen ? " [cen]" : "", is_logic ? " [logic]" : "", fanout);
is_reset ? " [reset]" : "",
is_cen ? " [cen]" : "",
is_logic ? " [logic]" : "",
fanout);
std::string glb_name = net->name.str(ctx) + std::string("_$glb_") + (is_reset ? "sr" : (is_cen ? "ce" : "clk")); std::string glb_name = net->name.str(ctx) + std::string("_$glb_") + (is_reset ? "sr" : (is_cen ? "ce" : "clk"));
std::unique_ptr<CellInfo> gb = create_ice_cell(ctx, ctx->id("SB_GB"), "$gbuf_" + glb_name); std::unique_ptr<CellInfo> gb = create_ice_cell(ctx, ctx->id("SB_GB"), "$gbuf_" + glb_name);

6
json/jsonparse.cc
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@ -594,7 +594,11 @@ void json_import_cell(Context *ctx, string modname, const std::vector<IdString>
if (type == PORT_IN || type == PORT_INOUT) { if (type == PORT_IN || type == PORT_INOUT) {
net->users.push_back(pr); net->users.push_back(pr);
} else if (type == PORT_OUT) { } else if (type == PORT_OUT) {
assert(net->driver.cell == nullptr); if (net->driver.cell != nullptr)
log_error("multiple drivers on net '%s' (%s.%s and %s.%s)\n",
net->name.c_str(ctx), net->driver.cell->name.c_str(ctx),
net->driver.port.c_str(ctx), pr.cell->name.c_str(ctx),
pr.port.c_str(ctx));
net->driver = pr; net->driver = pr;
} }
} }