Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr

CMakeLists.txt

@@ -96,7 +96,7 @@ foreach (family ${FAMILIES})
     foreach (target ${family_targets})
         # Include family-specific source files to all family targets and set defines appropriately
         target_include_directories(${target} PRIVATE ${family}/)
-        target_compile_definitions(${target} PRIVATE ARCH_${ufamily} ARCHNAME=${family} -DQT_NO_KEYWORDS)
+        target_compile_definitions(${target} PRIVATE NEXTPNR_NAMESPACE=nextpnr_${family} ARCH_${ufamily} ARCHNAME=${family} -DQT_NO_KEYWORDS)
         target_link_libraries(${target} LINK_PUBLIC ${Boost_LIBRARIES} ${PYTHON_LIBRARIES} ${GUI_LIBRARY_FILES})
     endforeach (target)
 

common/design.h

@@ -24,6 +24,8 @@
 #error Include "design.h" via "nextpnr.h" only.
 #endif
 
+NEXTPNR_NAMESPACE_BEGIN
+
 struct CellInfo;
 
 struct PortRef
@@ -81,4 +83,6 @@ struct Design
     std::unordered_map<IdString, CellInfo *> cells;
 };
 
+NEXTPNR_NAMESPACE_END
+
 #endif

common/design_utils.cc

@@ -19,6 +19,8 @@
 
 #include "design_utils.h"
 
+NEXTPNR_NAMESPACE_BEGIN
+
 void replace_port(CellInfo *old_cell, IdString old_name, CellInfo *rep_cell,
                   IdString rep_name)
 {
@@ -46,3 +48,5 @@ void replace_port(CellInfo *old_cell, IdString old_name, CellInfo *rep_cell,
         assert(false);
     }
 }
+
+NEXTPNR_NAMESPACE_END

common/design_utils.h

@@ -21,6 +21,9 @@
 
 #ifndef DESIGN_UTILS_H
 #define DESIGN_UTILS_H
+
+NEXTPNR_NAMESPACE_BEGIN
+
 /*
 Utilities for design manipulation, intended for use inside packing algorithms
  */
@@ -65,4 +68,6 @@ CellInfo *net_driven_by(NetInfo *net, F1 cell_pred, IdString port)
     }
 }
 
+NEXTPNR_NAMESPACE_END
+
 #endif

common/handle_error.cc

@@ -1,8 +1,11 @@
 #include <Python.h>
 #include <boost/python.hpp>
+#include "nextpnr.h"
 
 namespace py = boost::python;
 
+NEXTPNR_NAMESPACE_BEGIN
+
 // Parses the value of the active python exception
 // NOTE SHOULD NOT BE CALLED IF NO EXCEPTION
 std::string parse_python_exception()
@@ -56,3 +59,5 @@ std::string parse_python_exception()
     }
     return ret;
 }
+
+NEXTPNR_NAMESPACE_END

common/log.cc

@@ -28,6 +28,8 @@
 
 #include "log.h"
 
+NEXTPNR_NAMESPACE_BEGIN
+
 std::vector<FILE *> log_files;
 std::vector<std::ostream *> log_streams;
 FILE *log_errfile = NULL;
@@ -233,3 +235,5 @@ void log_flush()
 void log_cell(CellInfo *cell, std::string indent) {}
 
 void log_net(NetInfo *net, std::string indent) {}
+
+NEXTPNR_NAMESPACE_END

common/log.h

@@ -34,6 +34,8 @@
 #define NXP_NORETURN
 #define NXP_ATTRIBUTE(...) __attribute__((__VA_ARGS__))
 
+NEXTPNR_NAMESPACE_BEGIN
+
 struct log_cmd_error_exception
 {
 };
@@ -99,4 +101,6 @@ static inline void log_assert_worker(bool cond, const char *expr,
 #define log_ping()                                                             \
     log("-- %s:%d %s --\n", __FILE__, __LINE__, __PRETTY_FUNCTION__)
 
+NEXTPNR_NAMESPACE_END
+
 #endif

common/nextpnr.h

@@ -27,42 +27,40 @@
 #ifndef NEXTPNR_H
 #define NEXTPNR_H
 
+#ifdef NEXTPNR_NAMESPACE
+#define NEXTPNR_NAMESPACE_PREFIX NEXTPNR_NAMESPACE::
+#define NEXTPNR_NAMESPACE_BEGIN namespace NEXTPNR_NAMESPACE {
+#define NEXTPNR_NAMESPACE_END }
+#define USING_NEXTPNR_NAMESPACE using namespace NEXTPNR_NAMESPACE;
+#else
+#define NEXTPNR_NAMESPACE_PREFIX
+#define NEXTPNR_NAMESPACE_BEGIN
+#define NEXTPNR_NAMESPACE_END
+#define USING_NEXTPNR_NAMESPACE
+#endif
+
+NEXTPNR_NAMESPACE_BEGIN
+
 // replace with proper IdString later
 typedef std::string IdString;
 
 struct GraphicElement
 {
-    // This will control colour, and there should be separate
-    // visibility controls in some cases also
-    enum
-    {
-        // Wires entirely inside tiles, e.g. between switchbox and bels
-        G_LOCAL_WIRES,
-        // Standard inter-tile routing
-        G_GENERAL_WIRES,
-        // Special inter-tile wires, e.g. carry chains
-        G_DEDICATED_WIRES,
-        G_BEL_OUTLINE,
-        G_SWITCHBOX_OUTLINE,
-        G_TILE_OUTLINE,
-        G_BEL_PINS,
-        G_SWITCHBOX_PINS,
-        G_BEL_MISC,
-        G_TILE_MISC,
-    } style;
-
     enum
     {
+        G_NONE,
         G_LINE,
         G_BOX,
         G_CIRCLE,
         G_LABEL
-    } type;
+    } type = G_NONE;
 
-    float x1, y1, x2, y2, z;
+    float x1 = 0, y1 = 0, x2 = 0, y2 = 0, z = 0;
     std::string text;
 };
 
+NEXTPNR_NAMESPACE_END
+
 #include "chip.h"
 #include "design.h"
 

common/place.cc

@@ -32,6 +32,8 @@
 #include "log.h"
 #include "place.h"
 
+NEXTPNR_NAMESPACE_BEGIN
+
 void place_design(Design *design)
 {
     std::set<IdString> types_used;
@@ -117,3 +119,5 @@ void place_design(Design *design)
         }
     }
 }
+
+NEXTPNR_NAMESPACE_END

common/place.h

@@ -21,6 +21,10 @@
 
 #include "nextpnr.h"
 
+NEXTPNR_NAMESPACE_BEGIN
+
 extern void place_design(Design *design);
 
+NEXTPNR_NAMESPACE_END
+
 #endif // PLACE_H

common/pybindings.cc

@@ -25,6 +25,8 @@
 
 #include <fstream>
 
+NEXTPNR_NAMESPACE_BEGIN
+
 // Required to determine concatenated module name (which differs for different
 // archs)
 #define PASTER(x, y) x##_##y
@@ -64,7 +66,6 @@ Design load_design_shim(std::string filename, ChipArgs args)
 BOOST_PYTHON_MODULE(MODULE_NAME)
 {
     class_<GraphicElement>("GraphicElement")
-            .def_readwrite("style", &GraphicElement::style)
             .def_readwrite("type", &GraphicElement::type)
             .def_readwrite("x1", &GraphicElement::x1)
             .def_readwrite("y1", &GraphicElement::y1)
@@ -178,3 +179,5 @@ void execute_python_file(const char *python_file)
         std::cout << "Error in Python: " << perror_str << std::endl;
     }
 }
+
+NEXTPNR_NAMESPACE_END

common/pybindings.h

@@ -29,6 +29,11 @@
 #include <boost/python/suite/indexing/vector_indexing_suite.hpp>
 #include <stdexcept>
 #include <utility>
+
+#include "nextpnr.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
 using namespace boost::python;
 
 /*
@@ -110,8 +115,8 @@ void deinit_python();
 
 void execute_python_file(const char *python_file);
 
-std::string parse_python_exception();
-
 void arch_appendinittab();
 
+NEXTPNR_NAMESPACE_END
+
 #endif /* end of include guard: COMMON_PYBINDINGS_HH */

common/pycontainers.h

@@ -27,6 +27,9 @@
 #include <stdexcept>
 #include <type_traits>
 #include <utility>
+#include "nextpnr.h"
+
+NEXTPNR_NAMESPACE_BEGIN
 
 using namespace boost::python;
 
@@ -270,4 +273,6 @@ template <typename T> struct map_wrapper
     map_wrapper<t>().wrap(#name, #name "KeyValue", #name "KeyValueIter",       \
                           #name "Iterator")
 
+NEXTPNR_NAMESPACE_END
+
 #endif

common/route.cc

@@ -22,22 +22,23 @@
 #include "log.h"
 #include "route.h"
 
+NEXTPNR_NAMESPACE_BEGIN
+
 struct QueuedWire
 {
     WireId wire;
     PipId pip;
     DelayInfo delay;
-};
 
-namespace std {
+    struct Greater
-template <> struct greater<QueuedWire>
+    {
-{
+        bool operator()(const QueuedWire &lhs, const QueuedWire &rhs) const
-    bool operator()(const QueuedWire &lhs, const QueuedWire &rhs) const noexcept
+                noexcept
         {
             return lhs.delay.avgDelay() > rhs.delay.avgDelay();
         }
+    };
 };
-} // namespace std
 
 void route_design(Design *design)
 {
@@ -99,7 +100,7 @@ void route_design(Design *design)
 
             std::unordered_map<WireId, QueuedWire> visited;
             std::priority_queue<QueuedWire, std::vector<QueuedWire>,
-                                std::greater<QueuedWire>>
+                                QueuedWire::Greater>
                     queue;
 
             for (auto &it : src_wires) {
@@ -135,7 +136,7 @@ void route_design(Design *design)
 
                     if (next_qw.wire == dst_wire) {
                         std::priority_queue<QueuedWire, std::vector<QueuedWire>,
-                                            std::greater<QueuedWire>>
+                                            QueuedWire::Greater>
                                 empty_queue;
                         std::swap(queue, empty_queue);
                         break;
@@ -169,3 +170,5 @@ void route_design(Design *design)
         }
     }
 }
+
+NEXTPNR_NAMESPACE_END

common/route.h

@@ -22,6 +22,10 @@
 
 #include "design.h"
 
+NEXTPNR_NAMESPACE_BEGIN
+
 extern void route_design(Design *design);
 
+NEXTPNR_NAMESPACE_END
+
 #endif // ROUTE_H

common/rulecheck.cc

@@ -3,6 +3,8 @@
 #include "log.h"
 #include "nextpnr.h"
 
+NEXTPNR_NAMESPACE_BEGIN
+
 bool check_all_nets_driven(Design *design)
 {
     const bool debug = false;
@@ -70,3 +72,5 @@ bool check_all_nets_driven(Design *design)
         log_info("  Verified!\n");
     return true;
 }
+
+NEXTPNR_NAMESPACE_END

dummy/arch_place.cc

@@ -19,7 +19,11 @@
 
 #include "arch_place.h"
 
+NEXTPNR_NAMESPACE_BEGIN
+
 bool isValidBelForCell(Design *design, CellInfo *cell, BelId bel)
 {
     return true;
 }
+
+NEXTPNR_NAMESPACE_END

dummy/arch_place.h

@@ -22,6 +22,8 @@
 
 #include "nextpnr.h"
 
+NEXTPNR_NAMESPACE_BEGIN
+
 // Architecure-specific placement functions
 
 // Whether or not a given cell can be placed at a given Bel
@@ -29,4 +31,6 @@
 // such as conflicting set/reset signals, etc
 bool isValidBelForCell(Design *design, CellInfo *cell, BelId bel);
 
+NEXTPNR_NAMESPACE_END
+
 #endif

dummy/chip.cc

@@ -19,6 +19,8 @@
 
 #include "nextpnr.h"
 
+NEXTPNR_NAMESPACE_BEGIN
+
 Chip::Chip(ChipArgs) {}
 
 std::string Chip::getChipName() { return "Dummy"; }
@@ -156,3 +158,5 @@ std::vector<GraphicElement> Chip::getFrameGraphics() const
     static std::vector<GraphicElement> ret;
     return ret;
 }
+
+NEXTPNR_NAMESPACE_END

dummy/chip.h

@@ -24,6 +24,8 @@
 #error Include "chip.h" via "nextpnr.h" only.
 #endif
 
+NEXTPNR_NAMESPACE_BEGIN
+
 struct DelayInfo
 {
     float delay = 0;
@@ -116,4 +118,6 @@ struct Chip
     std::vector<GraphicElement> getFrameGraphics() const;
 };
 
+NEXTPNR_NAMESPACE_END
+
 #endif

dummy/main.cc

@@ -23,6 +23,8 @@
 #include "mainwindow.h"
 #include "nextpnr.h"
 
+USING_NEXTPNR_NAMESPACE
+
 int main(int argc, char *argv[])
 {
     Design design(ChipArgs{});

dummy/pybindings.cc

@@ -21,4 +21,8 @@
 #include "pybindings.h"
 #include "nextpnr.h"
 
+NEXTPNR_NAMESPACE_BEGIN
+
 void arch_wrap_python() { class_<ChipArgs>("ChipArgs"); }
+
+NEXTPNR_NAMESPACE_END

frontend/json/jsonparse.cc

@@ -29,6 +29,8 @@
 #include <string>
 #include "nextpnr.h"
 
+NEXTPNR_NAMESPACE_BEGIN
+
 extern bool check_all_nets_driven(Design *design);
 
 namespace JsonParser {
@@ -700,3 +702,5 @@ void parse_json_file(std::istream *&f, std::string &filename, Design *design)
     auto *parser = new JsonParser::JsonFrontend();
     parser->execute(f, filename, design);
 }
+
+NEXTPNR_NAMESPACE_END

frontend/json/jsonparse.h

@@ -24,6 +24,10 @@
 #include <string>
 #include "nextpnr.h"
 
+NEXTPNR_NAMESPACE_BEGIN
+
 extern void parse_json_file(std::istream *&, std::string &, Design *);
 
+NEXTPNR_NAMESPACE_END
+
 #endif

gui/fpgaviewwidget.h

@@ -7,6 +7,9 @@
 #include <QPainter>
 #include "nextpnr.h"
 
+// FIXME
+USING_NEXTPNR_NAMESPACE
+
 class FPGAViewWidget : public QOpenGLWidget, protected QOpenGLFunctions
 {
     Q_OBJECT
@@ -45,4 +48,5 @@ class FPGAViewWidget : public QOpenGLWidget, protected QOpenGLFunctions
     QPoint m_lastPos;
     Design *design;
 };
+
 #endif

gui/mainwindow.h

@@ -6,6 +6,9 @@
 
 #include <QMainWindow>
 
+// FIXME
+USING_NEXTPNR_NAMESPACE
+
 namespace Ui {
 class MainWindow;
 }

ice40/arch_place.cc

@@ -19,6 +19,8 @@
 
 #include "arch_place.h"
 
+NEXTPNR_NAMESPACE_BEGIN
+
 static bool logicCellsCompatible(const std::vector<const CellInfo *> &cells)
 {
     bool dffs_exist = false, dffs_neg = false;
@@ -87,3 +89,5 @@ bool isValidBelForCell(Design *design, CellInfo *cell, BelId bel)
         return true;
     }
 }
+
+NEXTPNR_NAMESPACE_END

ice40/arch_place.h

@@ -23,9 +23,13 @@
 #include "nextpnr.h"
 // Architecure-specific placement functions
 
+NEXTPNR_NAMESPACE_BEGIN
+
 // Whether or not a given cell can be placed at a given Bel
 // This is not intended for Bel type checks, but finer-grained constraints
 // such as conflicting set/reset signals, etc
 bool isValidBelForCell(Design *design, CellInfo *cell, BelId bel);
 
+NEXTPNR_NAMESPACE_END
+
 #endif

ice40/bitstream.cc

@@ -20,6 +20,8 @@
 #include "bitstream.h"
 #include <vector>
 
+NEXTPNR_NAMESPACE_BEGIN
+
 inline TileType tile_at(const Chip &chip, int x, int y)
 {
     return chip.chip_info.tile_grid[y * chip.chip_info.width + x];
@@ -311,3 +313,5 @@ void write_asc(const Design &design, std::ostream &out)
         }
     }
 }
+
+NEXTPNR_NAMESPACE_END

ice40/bitstream.h

@@ -23,6 +23,10 @@
 #include <iostream>
 #include "nextpnr.h"
 
+NEXTPNR_NAMESPACE_BEGIN
+
 void write_asc(const Design &design, std::ostream &out);
 
+NEXTPNR_NAMESPACE_END
+
 #endif

ice40/cells.cc

@@ -21,6 +21,8 @@
 #include "design_utils.h"
 #include "log.h"
 
+NEXTPNR_NAMESPACE_BEGIN
+
 static void add_port(CellInfo *cell, IdString name, PortType dir)
 {
     cell->ports[name] = PortInfo{name, nullptr, dir};
@@ -125,3 +127,5 @@ void dff_to_lc(CellInfo *dff, CellInfo *lc, bool pass_thru_lut)
 
     replace_port(dff, "Q", lc, "O");
 }
+
+NEXTPNR_NAMESPACE_END

ice40/cells.h

@@ -22,6 +22,8 @@
 #ifndef ICE40_CELLS_H
 #define ICE40_CELLS_H
 
+NEXTPNR_NAMESPACE_BEGIN
+
 // Create a standard iCE40 cell and return it
 // Name will be automatically assigned if not specified
 CellInfo *create_ice_cell(Design *design, IdString type,
@@ -56,4 +58,6 @@ void lut_to_lc(CellInfo *lut, CellInfo *lc, bool no_dff = true);
 // ignored
 void dff_to_lc(CellInfo *dff, CellInfo *lc, bool pass_thru_lut = false);
 
+NEXTPNR_NAMESPACE_END
+
 #endif

ice40/chip.cc

@@ -20,6 +20,8 @@
 #include "log.h"
 #include "nextpnr.h"
 
+NEXTPNR_NAMESPACE_BEGIN
+
 // -----------------------------------------------------------------------
 
 IdString belTypeToId(BelType type)
@@ -347,3 +349,5 @@ std::vector<GraphicElement> Chip::getFrameGraphics() const
 
     return ret;
 }
+
+NEXTPNR_NAMESPACE_END

ice40/chip.h

@@ -24,6 +24,8 @@
 #error Include "chip.h" via "nextpnr.h" only.
 #endif
 
+NEXTPNR_NAMESPACE_BEGIN
+
 struct DelayInfo
 {
     float delay = 0;
@@ -210,32 +212,36 @@ struct BelPin
     PortPin pin;
 };
 
+NEXTPNR_NAMESPACE_END
+
 namespace std {
-template <> struct hash<BelId>
+template <> struct hash<NEXTPNR_NAMESPACE_PREFIX BelId>
 {
-    std::size_t operator()(const BelId &bel) const noexcept
+    std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX BelId &bel) const noexcept
     {
         return bel.index;
     }
 };
 
-template <> struct hash<WireId>
+template <> struct hash<NEXTPNR_NAMESPACE_PREFIX WireId>
 {
-    std::size_t operator()(const WireId &wire) const noexcept
+    std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX WireId &wire) const noexcept
     {
         return wire.index;
     }
 };
 
-template <> struct hash<PipId>
+template <> struct hash<NEXTPNR_NAMESPACE_PREFIX PipId>
 {
-    std::size_t operator()(const PipId &wire) const noexcept
+    std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX PipId &wire) const noexcept
     {
         return wire.index;
     }
 };
 } // namespace std
 
+NEXTPNR_NAMESPACE_BEGIN
+
 // -----------------------------------------------------------------------
 
 struct BelIterator
@@ -679,4 +685,6 @@ struct Chip
     std::vector<GraphicElement> getFrameGraphics() const;
 };
 
+NEXTPNR_NAMESPACE_END
+
 #endif

ice40/chipdb.py

@@ -312,6 +312,8 @@ elif dev_name == "5k":
     add_bel_gb(19,  0, 7)
 
 print('#include "nextpnr.h"')
+print('namespace {')
+print('USING_NEXTPNR_NAMESPACE')
 
 for bel in range(len(bel_name)):
     print("static BelWirePOD bel_wires_%d[%d] = {" % (bel, len(bel_wires[bel])))
@@ -319,7 +321,7 @@ for bel in range(len(bel_name)):
         print("  {%d, PIN_%s}%s" % (bel_wires[bel][i] + ("," if i+1 < len(bel_wires[bel]) else "",)))
     print("};")
 
-print("BelInfoPOD bel_data_%s[%d] = {" % (dev_name, len(bel_name)))
+print("static BelInfoPOD bel_data_%s[%d] = {" % (dev_name, len(bel_name)))
 for bel in range(len(bel_name)):
     print("  {\"%s\", TYPE_%s, %d, bel_wires_%d, %d, %d, %d}%s" % (bel_name[bel], bel_type[bel],
             len(bel_wires[bel]), bel, bel_pos[bel][0], bel_pos[bel][1], bel_pos[bel][2],
@@ -458,8 +460,13 @@ print("static TileType tile_grid_%s[%d] = {" % (dev_name, len(tilegrid)))
 print(",\n".join(tilegrid))
 print("};")
 
+print('}')
+print('NEXTPNR_NAMESPACE_BEGIN')
+
 print("ChipInfoPOD chip_info_%s = {" % dev_name)
 print("  %d, %d, %d, %d, %d, %d," % (dev_width, dev_height, len(bel_name), num_wires, len(pipinfo), len(switchinfo)))
 print("  bel_data_%s, wire_data_%s, pip_data_%s," % (dev_name, dev_name, dev_name))
 print("  tile_grid_%s, &bits_info_%s" % (dev_name, dev_name))
 print("};")
+
+print('NEXTPNR_NAMESPACE_END')

ice40/family.cmake

@@ -11,6 +11,7 @@ set(DB_PY ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdb.py)
 file(MAKE_DIRECTORY ice40/chipdbs/)
 add_library(ice40_chipdb OBJECT ice40/chipdbs/)
 target_compile_options(ice40_chipdb PRIVATE -g0 -O0 -w)
+target_compile_definitions(ice40_chipdb PRIVATE NEXTPNR_NAMESPACE=nextpnr_${family})
 target_include_directories(ice40_chipdb PRIVATE ${family}/)
 foreach (dev ${devices})
     set(DEV_TXT_DB /usr/local/share/icebox/chipdb-${dev}.txt)

ice40/pack.cc

@@ -25,6 +25,8 @@
 
 #include <unordered_set>
 
+NEXTPNR_NAMESPACE_BEGIN
+
 // Pack LUTs and LUT-FF pairs
 static void pack_lut_lutffs(Design *design)
 {
@@ -120,3 +122,5 @@ void pack_design(Design *design)
     pack_lut_lutffs(design);
     pack_nonlut_ffs(design);
 }
+
+NEXTPNR_NAMESPACE_END

ice40/pack.h

@@ -22,6 +22,10 @@
 
 #include "nextpnr.h"
 
+NEXTPNR_NAMESPACE_BEGIN
+
 void pack_design(Design *design);
 
+NEXTPNR_NAMESPACE_END
+
 #endif // ROUTE_H

ice40/pybindings.cc

@@ -21,6 +21,8 @@
 #include "pybindings.h"
 #include "nextpnr.h"
 
+NEXTPNR_NAMESPACE_BEGIN
+
 void arch_wrap_python()
 {
     class_<ChipArgs>("ChipArgs").def_readwrite("type", &ChipArgs::type);
@@ -80,3 +82,5 @@ void arch_wrap_python()
     WRAP_RANGE(AllPip);
     WRAP_RANGE(Pip);
 }
+
+NEXTPNR_NAMESPACE_END