mistral: Add some packing logic based on nexus
Signed-off-by: gatecat <gatecat@ds0.me>
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gatecat
parent
3fc5396063
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595b354184
33
mistral/archdefs.cc
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33
mistral/archdefs.cc
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@ -0,0 +1,33 @@
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/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2021 gatecat <gatecat@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "nextpnr.h"
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NEXTPNR_NAMESPACE_BEGIN
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CellPinState ArchCellInfo::get_pin_state(IdString pin) const
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{
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auto fnd = pin_data.find(pin);
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if (fnd != pin_data.end())
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return fnd->second.state;
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else
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return PIN_SIG;
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}
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NEXTPNR_NAMESPACE_END
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@ -192,6 +192,8 @@ struct ArchCellInfo : BaseClusterInfo
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};
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std::unordered_map<IdString, ArchPinInfo> pin_data;
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CellPinState get_pin_state(IdString pin) const;
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};
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NEXTPNR_NAMESPACE_END
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@ -58,6 +58,9 @@ X(MISTRAL_NOT)
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X(MISTRAL_BUF)
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X(MISTRAL_CONST)
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X(MISTRAL_ALUT_ARITH)
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X(LUT)
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X(LUT0)
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X(LUT1)
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X(D0)
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X(D1)
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@ -65,4 +68,7 @@ X(CI)
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X(CO)
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X(SO)
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X(WIRE)
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X(WIRE)
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X(GND)
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X(VCC)
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162
mistral/pack.cc
162
mistral/pack.cc
@ -17,18 +17,176 @@
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*
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*/
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#include "design_utils.h"
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#include "log.h"
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#include "nextpnr.h"
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#include "util.h"
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NEXTPNR_NAMESPACE_BEGIN
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namespace {
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struct MistralPacker
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{
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MistralPacker(Context *ctx) : ctx(ctx){};
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Context *ctx;
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NetInfo *gnd_net, *vcc_net;
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void init_constant_nets()
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{
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CellInfo *gnd_drv = ctx->createCell(ctx->id("$PACKER_GND_DRV"), id_MISTRAL_CONST);
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gnd_drv->params[id_LUT] = 0;
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gnd_drv->addOutput(id_Q);
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CellInfo *vcc_drv = ctx->createCell(ctx->id("$PACKER_VCC_DRV"), id_MISTRAL_CONST);
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vcc_drv->params[id_LUT] = 1;
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vcc_drv->addOutput(id_Q);
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gnd_net = ctx->createNet(ctx->id("$PACKER_GND_NET"));
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vcc_net = ctx->createNet(ctx->id("$PACKER_VCC_NET"));
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connect_port(ctx, gnd_net, gnd_drv, id_Q);
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connect_port(ctx, vcc_net, vcc_drv, id_Q);
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}
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CellPinState get_pin_needed_muxval(CellInfo *cell, IdString port)
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{
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NetInfo *net = get_net_or_empty(cell, port);
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if (net == nullptr || net->driver.cell == nullptr) {
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// Pin is disconnected
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// If a mux value exists already, honour it
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CellPinState exist_mux = cell->get_pin_state(port);
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if (exist_mux != PIN_SIG)
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return exist_mux;
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// Otherwise, look up the default value and use that
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CellPinStyle pin_style = ctx->get_cell_pin_style(cell, port);
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if ((pin_style & PINDEF_MASK) == PINDEF_0)
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return PIN_0;
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else if ((pin_style & PINDEF_MASK) == PINDEF_1)
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return PIN_1;
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else
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return PIN_SIG;
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}
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// Look to see if the driver is an inverter or constant
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IdString drv_type = net->driver.cell->type;
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if (drv_type == id_MISTRAL_NOT)
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return PIN_INV;
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else if (drv_type == id_GND)
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return PIN_0;
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else if (drv_type == id_VCC)
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return PIN_1;
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else
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return PIN_SIG;
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}
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void uninvert_port(CellInfo *cell, IdString port)
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{
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// Rewire a port so it is driven by the input to an inverter
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NetInfo *net = get_net_or_empty(cell, port);
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NPNR_ASSERT(net != nullptr && net->driver.cell != nullptr && net->driver.cell->type == id_MISTRAL_NOT);
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CellInfo *inv = net->driver.cell;
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disconnect_port(ctx, cell, port);
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NetInfo *inv_a = get_net_or_empty(inv, id_A);
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if (inv_a != nullptr) {
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connect_port(ctx, inv_a, cell, port);
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}
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}
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void process_inv_constants(CellInfo *cell)
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{
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// TODO: we might need to create missing inputs here in some cases so we can tie them to the correct constant?
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// Fold inverters and constants into a cell
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for (auto &port : cell->ports) {
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// Iterate over all inputs
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if (port.second.type != PORT_IN)
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continue;
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IdString port_name = port.first;
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CellPinState req_mux = get_pin_needed_muxval(cell, port_name);
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if (req_mux == PIN_SIG) {
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// No special setting required, ignore
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continue;
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}
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CellPinStyle pin_style = ctx->get_cell_pin_style(cell, port_name);
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if (req_mux == PIN_INV) {
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// Pin is inverted. If there is a hard inverter; then use it
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if (pin_style & PINOPT_INV) {
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uninvert_port(cell, port_name);
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cell->pin_data[port_name].state = PIN_INV;
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}
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} else if (req_mux == PIN_0 || req_mux == PIN_1) {
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// Pin is tied to a constant
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// If there is a hard constant option; use it
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if ((pin_style & int(req_mux)) == req_mux) {
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disconnect_port(ctx, cell, port_name);
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cell->pin_data[port_name].state = req_mux;
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} else {
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disconnect_port(ctx, cell, port_name);
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// There is no hard constant, we need to connect it to the relevant soft-constant net
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connect_port(ctx, (req_mux == PIN_1) ? vcc_net : gnd_net, cell, port_name);
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}
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}
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}
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}
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void trim_design()
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{
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// Remove unused inverters and high/low drivers
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std::vector<IdString> trim_cells;
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std::vector<IdString> trim_nets;
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for (auto cell : sorted(ctx->cells)) {
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CellInfo *ci = cell.second;
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if (ci->type != id_MISTRAL_NOT && ci->type != id_GND && ci->type != id_VCC)
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continue;
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IdString port = (ci->type == id_MISTRAL_NOT) ? id_Q : ci->type;
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NetInfo *out = get_net_or_empty(ci, port);
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if (out == nullptr) {
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trim_cells.push_back(ci->name);
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continue;
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}
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if (!out->users.empty())
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continue;
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disconnect_port(ctx, ci, id_A);
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trim_cells.push_back(ci->name);
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trim_nets.push_back(out->name);
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}
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for (IdString rem_net : trim_nets)
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ctx->nets.erase(rem_net);
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for (IdString rem_cell : trim_cells)
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ctx->cells.erase(rem_cell);
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}
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void pack_constants()
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{
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// Iterate through cells
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for (auto cell : sorted(ctx->cells)) {
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CellInfo *ci = cell.second;
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// Skip certain cells at this point
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if (ci->type != id_MISTRAL_NOT && ci->type != id_GND && ci->type != id_VCC)
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process_inv_constants(cell.second);
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}
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// Remove superfluous inverters and constant drivers
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trim_design();
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}
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void run()
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{
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init_constant_nets();
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pack_constants();
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}
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};
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}; // namespace
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bool Arch::pack()
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{
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// TODO:
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// - Insert constant driver LUTs
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// - Fold constants and inverters into cell pins
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// - Constrain IO
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MistralPacker packer(getCtx());
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packer.run();
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return true;
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}
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