tmg: Add net_timings, crit path and slack hist
This commit is contained in:
rowanG077
myrtle
parent
8b51674a6b
commit
596873c302
@ -356,9 +356,14 @@ struct TimingResult
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dict<IdString, CriticalPath> clock_paths;
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// Cross-domain critical paths
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std::vector<CriticalPath> xclock_paths;
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// Domains with no interior paths
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pool<IdString> empty_paths;
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// Detailed net timing data
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dict<IdString, std::vector<NetSinkTiming>> detailed_net_timings;
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// Histogram of delays
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dict<int, unsigned> delay_frequency;
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};
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// Represents the contents of a non-leaf cell in a design
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@ -50,17 +50,17 @@ TimingAnalyser::TimingAnalyser(Context *ctx) : ctx(ctx)
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async_clock_id = 0;
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};
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void TimingAnalyser::setup()
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void TimingAnalyser::setup(bool update_net_timings, bool update_histogram, bool update_crit_paths, bool update_route_delays)
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{
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init_ports();
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get_cell_delays();
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topo_sort();
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setup_port_domains();
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identify_related_domains();
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run();
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run(update_net_timings, update_histogram, update_crit_paths, update_route_delays);
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}
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void TimingAnalyser::run(bool update_route_delays)
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void TimingAnalyser::run(bool update_net_timings, bool update_histogram, bool update_crit_paths, bool update_route_delays)
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{
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reset_times();
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if (update_route_delays)
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@ -69,6 +69,25 @@ void TimingAnalyser::run(bool update_route_delays)
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walk_backward();
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compute_slack();
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compute_criticality();
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// Ensure we clear all timing results if any of them has been marked as
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// as to be updated. This is done so we ensure it's not possible to have
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// timing_result which contains mixed reports
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if (update_net_timings || update_histogram || update_crit_paths) {
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ctx->timing_result = TimingResult();
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}
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if (update_net_timings) {
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build_detailed_net_timing_report();
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}
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if (update_histogram) {
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build_slack_histogram_report();
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}
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if (update_crit_paths) {
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build_crit_path_reports();
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}
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}
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void TimingAnalyser::init_ports()
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@ -640,19 +659,21 @@ void TimingAnalyser::walk_backward()
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}
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}
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dict<domain_id_t, delay_t> TimingAnalyser::max_delay_by_domain()
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dict<domain_id_t, delay_t> TimingAnalyser::max_delay_by_domain_pairs()
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{
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dict<domain_id_t, delay_t> domain_delay;
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for (auto p : topological_order) {
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auto &pd = ports.at(p);
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for (auto &req : pd.required) {
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if (pd.arrival.count(req.first)) {
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if (domains.at(req.first).key.is_async())
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continue;
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auto &arr = pd.arrival.at(req.first);
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delay_t delay = arr.value.maxDelay() - req.second.value.minDelay();
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if (!domain_delay.count(req.first) || domain_delay.at(req.first) < delay)
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domain_delay[req.first] = delay;
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auto &capture = req.first;
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for (auto &arr : pd.arrival) {
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auto &launch = arr.first;
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auto dp = domain_pair_id(launch, capture);
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delay_t delay = arr.second.value.maxDelay() - req.second.value.minDelay();
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if (!domain_delay.count(dp) || domain_delay.at(dp) < delay)
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domain_delay[dp] = delay;
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}
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}
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}
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@ -703,6 +724,7 @@ void TimingAnalyser::compute_criticality()
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{
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for (auto p : topological_order) {
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auto &pd = ports.at(p);
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for (auto &pdp : pd.domain_pairs) {
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auto &dp = domain_pairs.at(pdp.first);
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// Do not set criticality for asynchronous paths
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@ -719,13 +741,51 @@ void TimingAnalyser::compute_criticality()
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}
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}
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std::vector<CellPortKey> TimingAnalyser::get_failing_eps(domain_id_t domain_pair, int count)
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void TimingAnalyser::build_detailed_net_timing_report()
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{
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std::vector<CellPortKey> failing_eps;
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auto &net_timings = ctx->timing_result.detailed_net_timings;
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for (domain_id_t dom_id = 0; dom_id < domain_id_t(domains.size()); ++dom_id) {
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auto &dom = domains.at(dom_id);
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for (auto &ep : dom.endpoints) {
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auto &pd = ports.at(ep.first);
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const NetInfo *net = port_info(ep.first).net;
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for (auto &arr : pd.arrival) {
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auto &launch = domains.at(arr.first).key;
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for (auto &req : pd.required) {
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auto &capture = domains.at(req.first).key;
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NetSinkTiming sink_timing;
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sink_timing.clock_pair = ClockPair {
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.start = ClockEvent {
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.clock = launch.clock,
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.edge = launch.edge
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},
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.end = ClockEvent {
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.clock = capture.clock,
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.edge = capture.edge
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}
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};
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sink_timing.cell_port = std::make_pair(pd.cell_port.cell, pd.cell_port.port);
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sink_timing.delay = arr.second.value.max_delay;
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log_info("update net_timings: %s: %f\n", net->name.c_str(ctx), (float) sink_timing.delay);
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net_timings[net->name].push_back(sink_timing);
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}
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}
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}
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}
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}
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std::vector<CellPortKey> TimingAnalyser::get_worst_eps(domain_id_t domain_pair, int count)
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{
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std::vector<CellPortKey> worst_eps;
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delay_t last_slack = std::numeric_limits<delay_t>::min();
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auto &dp = domain_pairs.at(domain_pair);
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auto &cap_d = domains.at(dp.key.capture);
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while (int(failing_eps.size()) < count) {
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while (int(worst_eps.size()) < count) {
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CellPortKey next;
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delay_t next_slack = std::numeric_limits<delay_t>::max();
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for (auto ep : cap_d.endpoints) {
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@ -740,35 +800,10 @@ std::vector<CellPortKey> TimingAnalyser::get_failing_eps(domain_id_t domain_pair
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}
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if (next == CellPortKey())
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break;
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failing_eps.push_back(next);
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worst_eps.push_back(next);
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last_slack = next_slack;
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}
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return failing_eps;
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}
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std::string tgp_to_string2(TimingPortClass c) {
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switch (c) {
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case TMG_CLOCK_INPUT:
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return "TMG_CLOCK_INPUT";
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case TMG_GEN_CLOCK:
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return "TMG_GEN_CLOCK";
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case TMG_REGISTER_INPUT:
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return "TMG_REGISTER_INPUT";
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case TMG_REGISTER_OUTPUT:
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return "TMG_REGISTER_OUTPUT";
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case TMG_COMB_INPUT:
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return "TMG_COMB_INPUT";
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case TMG_COMB_OUTPUT:
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return "TMG_COMB_OUTPUT";
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case TMG_STARTPOINT:
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return "TMG_STARTPOINT";
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case TMG_ENDPOINT:
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return "TMG_ENDPOINT";
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case TMG_IGNORE:
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return "TMG_IGNORE";
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}
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return "UNKNOWN";
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return worst_eps;
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}
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CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair, CellPortKey endpoint)
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@ -852,8 +887,6 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
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}
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}
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log_info("building critical path report for clocks: %s -> %s\n", launch.clock.c_str(ctx), capture.clock.c_str(ctx));
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for (auto sink : crit_path) {
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auto sink_cell = sink.cell;
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auto &port = sink_cell->ports.at(sink.port);
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@ -861,10 +894,6 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
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auto &driver = net->driver;
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auto driver_cell = driver.cell;
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auto clockInfo0 = ctx->getPortTimingClass(driver_cell, driver.port, clock_start);
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log_info("\t%s.%s, tmgPortClass: %s\n", sink_cell->name.c_str(ctx), port.name.c_str(ctx), tgp_to_string2(clockInfo0).c_str());
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CriticalPath::Segment seg_logic;
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DelayQuad comb_delay;
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@ -920,22 +949,25 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair,
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return report;
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}
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void TimingAnalyser::print_report()
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void TimingAnalyser::build_crit_path_reports()
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{
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dict<IdString, CriticalPath> clock_reports;
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std::vector<CriticalPath> xclock_reports;
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dict<IdString, ClockFmax> clock_fmax;
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std::set<IdString> empty_clocks;
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auto &clock_reports = ctx->timing_result.clock_paths;
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auto &xclock_reports = ctx->timing_result.xclock_paths;
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auto &clock_fmax = ctx->timing_result.clock_fmax;
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auto &empty_clocks = ctx->timing_result.empty_paths;
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auto &clock_delays_ctx = ctx->timing_result.clock_delays;
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auto delay_by_domain = max_delay_by_domain();
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auto delay_by_domain = max_delay_by_domain_pairs();
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auto uq_doms = ctx->timing_result.empty_paths;
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auto clock_pairs = std::vector<std::pair<ClockDomainKey, ClockDomainKey>>();
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for (int i = 0; i < int(domain_pairs.size()); i++) {
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auto &dp = domain_pairs.at(i);
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auto &launch = domains.at(dp.key.launch).key;
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auto &capture = domains.at(dp.key.capture).key;
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empty_clocks.insert(launch.clock);
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empty_clocks.insert(capture.clock);
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clock_pairs.emplace_back(std::make_pair(launch, capture));
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}
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for (int i = 0; i < int(domain_pairs.size()); i++) {
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@ -943,7 +975,7 @@ void TimingAnalyser::print_report()
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auto &launch = domains.at(dp.key.launch).key;
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auto &capture = domains.at(dp.key.capture).key;
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if (launch.clock != capture.clock || launch.clock == ctx->id("$async$"))
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if (launch.clock != capture.clock || launch.is_async())
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continue;
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auto path_delay = delay_by_domain.at(dp.key.launch);
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@ -957,9 +989,13 @@ void TimingAnalyser::print_report()
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Fmax = 500 / ctx->getDelayNS(path_delay);
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if (!clock_fmax.count(launch.clock) || Fmax < clock_fmax.at(launch.clock).achieved) {
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float target = ctx->setting<float>("target_freq") / 1e6;
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if (ctx->nets.at(launch.clock)->clkconstr)
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target = 1000 / ctx->getDelayNS(ctx->nets.at(launch.clock)->clkconstr->period.minDelay());
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clock_fmax[launch.clock].achieved = Fmax;
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clock_fmax[launch.clock].constraint = 0.0f; // Will be filled later
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auto worst_endpoint = get_failing_eps(i, 1).at(0);
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clock_fmax[launch.clock].constraint = target;
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auto worst_endpoint = get_worst_eps(i, 1).at(0);
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clock_reports[launch.clock] = build_critical_path_report(i, worst_endpoint);
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}
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}
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@ -969,17 +1005,13 @@ void TimingAnalyser::print_report()
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auto &launch = domains.at(dp.key.launch).key;
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auto &capture = domains.at(dp.key.capture).key;
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if (launch.clock == capture.clock && launch.clock == ctx->id("$async$"))
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if (launch.clock == capture.clock)
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continue;
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auto worst_endpoint = get_failing_eps(i, 1).at(0);
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auto worst_endpoint = get_worst_eps(i, 1).at(0);
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xclock_reports.emplace_back(build_critical_path_report(i, worst_endpoint));
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}
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if (clock_reports.empty() && xclock_reports.empty()) {
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log_info("No Fmax available; no interior timing paths found in design.\n");
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}
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std::sort(xclock_reports.begin(), xclock_reports.end(), [&](const CriticalPath &ra, const CriticalPath &rb) {
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const auto &a = ra.clock_pair;
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const auto &b = rb.clock_pair;
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@ -1008,13 +1040,13 @@ void TimingAnalyser::print_report()
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clock_fmax[clock.first].constraint = target;
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}
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clock_delays_ctx = clock_delays;
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}
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auto print_path = true;
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auto print_fmax =true;
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auto format_event = [&](const ClockEvent &e, int field_width = 0) {
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static std::string clock_event_name(const Context *ctx, const ClockDomainKey &e, int field_width = 0)
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{
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std::string value;
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if (e.clock == ctx->id("$async$"))
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if (e.clock == IdString() || e.clock == ctx->id("$async$"))
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value = std::string("<async>");
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else
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value = (e.edge == FALLING_EDGE ? std::string("negedge ") : std::string("posedge ")) + e.clock.str(ctx);
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@ -1023,293 +1055,39 @@ void TimingAnalyser::print_report()
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return value;
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};
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// Print critical paths
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if (print_path) {
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if (ctx->idstring_str_to_idx == nullptr) {
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log_info("global: ctx->idstring_str_to_idx is nullptr\n");
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} else {
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for (const auto& kv : *ctx->idstring_str_to_idx) {
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log_info("global: %s -> %d\n", kv.first.c_str(), kv.second);
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}
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}
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void TimingAnalyser::build_slack_histogram_report()
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{
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auto& slack_histogram = ctx->timing_result.slack_histogram;
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static auto print_net_source = [](Context* ctx, const NetInfo *net) {
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// Check if this net is annotated with a source list
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auto sources = net->attrs.find(ctx->id("src"));
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if (sources == net->attrs.end()) {
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// No sources for this net, can't print anything
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return;
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}
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for (domain_id_t dom_id = 0; dom_id < domain_id_t(domains.size()); ++dom_id) {
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for (auto &ep : domains.at(dom_id).endpoints) {
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auto &pd = ports.at(ep.first);
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// Sources are separated by pipe characters.
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// There is no guaranteed ordering on sources, so we just print all
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auto sourcelist = sources->second.as_string();
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std::vector<std::string> source_entries;
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size_t current = 0, prev = 0;
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while ((current = sourcelist.find("|", prev)) != std::string::npos) {
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source_entries.emplace_back(sourcelist.substr(prev, current - prev));
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prev = current + 1;
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}
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// Ensure we emplace the final entry
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source_entries.emplace_back(sourcelist.substr(prev, current - prev));
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for (auto &req : pd.required) {
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auto &capture = domains.at(req.first).key;
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for (auto &arr : pd.arrival) {
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auto &launch = domains.at(arr.first).key;
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// Iterate and print our source list at the correct indentation level
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log_info(" Defined in:\n");
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for (auto entry : source_entries) {
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log_info(" %s\n", entry.c_str());
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}
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};
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// A helper function for reporting one critical path
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auto print_path_report = [](Context* ctx, const CriticalPath &path) {
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delay_t total = 0, logic_total = 0, route_total = 0;
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log_info("curr total\n");
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for (const auto &segment : path.segments) {
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// log_info("processing segment %s\n", segment.net.c_str(ctx));
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total += segment.delay;
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if (segment.type == CriticalPath::Segment::Type::CLK_TO_Q ||
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segment.type == CriticalPath::Segment::Type::SOURCE ||
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segment.type == CriticalPath::Segment::Type::LOGIC ||
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segment.type == CriticalPath::Segment::Type::SETUP) {
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logic_total += segment.delay;
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const std::string type_name =
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(segment.type == CriticalPath::Segment::Type::SETUP) ? "Setup" : "Source";
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log_info("%4.1f %4.1f %s %s.%s\n", ctx->getDelayNS(segment.delay), ctx->getDelayNS(total),
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type_name.c_str(), segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
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} else if (segment.type == CriticalPath::Segment::Type::ROUTING) {
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route_total += segment.delay;
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const auto &driver = ctx->cells.at(segment.from.first);
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const auto &sink = ctx->cells.at(segment.to.first);
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auto driver_loc = ctx->getBelLocation(driver->bel);
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auto sink_loc = ctx->getBelLocation(sink->bel);
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log_info("%4.1f %4.1f Net %s (%d,%d) -> (%d,%d)\n", ctx->getDelayNS(segment.delay),
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ctx->getDelayNS(total), segment.net.c_str(ctx),
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driver_loc.x, driver_loc.y, sink_loc.x, sink_loc.y);
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log_info(" Sink %s.%s\n", segment.to.first.c_str(ctx), segment.to.second.c_str(ctx));
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const NetInfo *net = ctx->nets.at(segment.net).get();
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if (ctx->verbose) {
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PortRef sink_ref;
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sink_ref.cell = sink.get();
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sink_ref.port = segment.to.second;
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auto driver_wire = ctx->getNetinfoSourceWire(net);
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auto sink_wire = ctx->getNetinfoSinkWire(net, sink_ref, 0);
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log_info(" prediction: %f ns estimate: %f ns\n",
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ctx->getDelayNS(ctx->predictArcDelay(net, sink_ref)),
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ctx->getDelayNS(ctx->estimateDelay(driver_wire, sink_wire)));
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auto cursor = sink_wire;
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delay_t delay;
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while (driver_wire != cursor) {
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#ifdef ARCH_ECP5
|
||||
if (net->is_global)
|
||||
break;
|
||||
#endif
|
||||
auto it = net->wires.find(cursor);
|
||||
assert(it != net->wires.end());
|
||||
auto pip = it->second.pip;
|
||||
NPNR_ASSERT(pip != PipId());
|
||||
delay = ctx->getPipDelay(pip).maxDelay();
|
||||
log_info(" %1.3f %s\n", ctx->getDelayNS(delay), ctx->nameOfPip(pip));
|
||||
cursor = ctx->getPipSrcWire(pip);
|
||||
}
|
||||
}
|
||||
|
||||
if (!ctx->disable_critical_path_source_print) {
|
||||
print_net_source(ctx, net);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
log_info("%.1f ns logic, %.1f ns routing\n", ctx->getDelayNS(logic_total), ctx->getDelayNS(route_total));
|
||||
};
|
||||
|
||||
// Single domain paths
|
||||
for (auto &clock : clock_reports) {
|
||||
log_break();
|
||||
std::string start = clock.second.clock_pair.start.edge == FALLING_EDGE ? std::string("negedge")
|
||||
: std::string("posedge");
|
||||
std::string end =
|
||||
clock.second.clock_pair.end.edge == FALLING_EDGE ? std::string("negedge") : std::string("posedge");
|
||||
log_info("Critical path report for clock '%s' (%s -> %s):\n", clock.first.c_str(ctx), start.c_str(),
|
||||
end.c_str());
|
||||
auto &report = clock.second;
|
||||
print_path_report(ctx, report);
|
||||
}
|
||||
|
||||
// Cross-domain paths
|
||||
for (auto &report : xclock_reports) {
|
||||
log_break();
|
||||
std::string start = format_event(report.clock_pair.start);
|
||||
std::string end = format_event(report.clock_pair.end);
|
||||
log_info("Critical path report for cross-domain path '%s' -> '%s':\n", start.c_str(), end.c_str());
|
||||
print_path_report(ctx, report);
|
||||
}
|
||||
}
|
||||
|
||||
if (print_fmax) {
|
||||
log_break();
|
||||
|
||||
unsigned max_width = 0;
|
||||
for (auto &clock : clock_reports)
|
||||
max_width = std::max<unsigned>(max_width, clock.first.str(ctx).size());
|
||||
|
||||
for (auto &clock : clock_reports) {
|
||||
const auto &clock_name = clock.first.str(ctx);
|
||||
const int width = max_width - clock_name.size();
|
||||
|
||||
float fmax = clock_fmax[clock.first].achieved;
|
||||
float target = clock_fmax[clock.first].constraint;
|
||||
bool passed = target < fmax;
|
||||
|
||||
if (passed)
|
||||
log_info("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
|
||||
clock_name.c_str(), fmax, passed ? "PASS" : "FAIL", target);
|
||||
else if (bool_or_default(ctx->settings, ctx->id("timing/allowFail"), false))
|
||||
log_warning("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
|
||||
clock_name.c_str(), fmax, passed ? "PASS" : "FAIL", target);
|
||||
else
|
||||
log_nonfatal_error("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
|
||||
clock_name.c_str(), fmax, passed ? "PASS" : "FAIL", target);
|
||||
}
|
||||
log_break();
|
||||
|
||||
// All clock to clock delays
|
||||
const auto &clock_delays = get_clock_delays();
|
||||
|
||||
// Clock to clock delays for xpaths
|
||||
dict<ClockPair, delay_t> xclock_delays;
|
||||
for (auto &report : xclock_reports) {
|
||||
const auto &clock1_name = report.clock_pair.start.clock;
|
||||
const auto &clock2_name = report.clock_pair.end.clock;
|
||||
|
||||
const auto key = std::make_pair(clock1_name, clock2_name);
|
||||
if (clock_delays.count(key)) {
|
||||
xclock_delays[report.clock_pair] = clock_delays.at(key);
|
||||
}
|
||||
}
|
||||
|
||||
unsigned max_width_xca = 0;
|
||||
unsigned max_width_xcb = 0;
|
||||
for (auto &report : xclock_reports) {
|
||||
max_width_xca = std::max((unsigned)format_event(report.clock_pair.start).length(), max_width_xca);
|
||||
max_width_xcb = std::max((unsigned)format_event(report.clock_pair.end).length(), max_width_xcb);
|
||||
}
|
||||
|
||||
// Check and report xpath delays for related clocks
|
||||
if (!xclock_reports.empty()) {
|
||||
for (auto &report : xclock_reports) {
|
||||
const auto &clock_a = report.clock_pair.start.clock;
|
||||
const auto &clock_b = report.clock_pair.end.clock;
|
||||
|
||||
const auto key = std::make_pair(clock_a, clock_b);
|
||||
if (!clock_delays.count(key)) {
|
||||
// @gatecat: old timing analysis includes async path
|
||||
// The slack doesn' make much sense so I filter it out.
|
||||
if (launch.clock != capture.clock || launch.is_async())
|
||||
continue;
|
||||
|
||||
float clk_period = ctx->getDelayFromNS(1.0e9 / ctx->setting<float>("target_freq"));
|
||||
if (ctx->nets.at(launch.clock)->clkconstr)
|
||||
clk_period = ctx->nets.at(launch.clock)->clkconstr->period.minDelay();
|
||||
|
||||
if (launch.edge != capture.edge)
|
||||
clk_period = clk_period / 2;
|
||||
|
||||
delay_t delay = arr.second.value.maxDelay() - req.second.value.minDelay();
|
||||
delay_t slack = clk_period - delay;
|
||||
|
||||
int slack_ps = ctx->getDelayNS(slack) * 1000;
|
||||
slack_histogram[slack_ps]++;
|
||||
}
|
||||
|
||||
delay_t path_delay = 0;
|
||||
for (const auto &segment : report.segments) {
|
||||
path_delay += segment.delay;
|
||||
}
|
||||
|
||||
// Compensate path delay for clock-to-clock delay. If the
|
||||
// result is negative then only the latter matters. Otherwise
|
||||
// the compensated path delay is taken.
|
||||
auto clock_delay = clock_delays.at(key);
|
||||
path_delay -= clock_delay;
|
||||
|
||||
float fmax = std::numeric_limits<float>::infinity();
|
||||
if (path_delay < 0) {
|
||||
fmax = 1e3f / ctx->getDelayNS(clock_delay);
|
||||
} else if (path_delay > 0) {
|
||||
fmax = 1e3f / ctx->getDelayNS(path_delay);
|
||||
}
|
||||
|
||||
// Both clocks are related so they should have the same
|
||||
// frequency. However, they may get different constraints from
|
||||
// user input. In case of only one constraint preset take it,
|
||||
// otherwise get the worst case (min.)
|
||||
float target;
|
||||
if (clock_fmax.count(clock_a) && !clock_fmax.count(clock_b)) {
|
||||
target = clock_fmax.at(clock_a).constraint;
|
||||
} else if (!clock_fmax.count(clock_a) && clock_fmax.count(clock_b)) {
|
||||
target = clock_fmax.at(clock_b).constraint;
|
||||
} else {
|
||||
target = std::min(clock_fmax.at(clock_a).constraint, clock_fmax.at(clock_b).constraint);
|
||||
}
|
||||
|
||||
bool passed = target < fmax;
|
||||
|
||||
auto ev_a = format_event(report.clock_pair.start, max_width_xca);
|
||||
auto ev_b = format_event(report.clock_pair.end, max_width_xcb);
|
||||
|
||||
if (passed)
|
||||
log_info("Max frequency for %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(), ev_b.c_str(),
|
||||
fmax, passed ? "PASS" : "FAIL", target);
|
||||
else if (bool_or_default(ctx->settings, ctx->id("timing/allowFail"), false) ||
|
||||
bool_or_default(ctx->settings, ctx->id("timing/ignoreRelClk"), false))
|
||||
log_warning("Max frequency for %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(),
|
||||
ev_b.c_str(), fmax, passed ? "PASS" : "FAIL", target);
|
||||
else
|
||||
log_nonfatal_error("Max frequency for %s -> %s: %.02f MHz (%s at %.02f MHz)\n", ev_a.c_str(),
|
||||
ev_b.c_str(), fmax, passed ? "PASS" : "FAIL", target);
|
||||
}
|
||||
log_break();
|
||||
}
|
||||
|
||||
// Report clock delays for xpaths
|
||||
if (!clock_delays.empty()) {
|
||||
for (auto &pair : xclock_delays) {
|
||||
auto ev_a = format_event(pair.first.start, max_width_xca);
|
||||
auto ev_b = format_event(pair.first.end, max_width_xcb);
|
||||
|
||||
delay_t delay = pair.second;
|
||||
if (pair.first.start.edge != pair.first.end.edge) {
|
||||
delay /= 2;
|
||||
}
|
||||
|
||||
log_info("Clock to clock delay %s -> %s: %0.02f ns\n", ev_a.c_str(), ev_b.c_str(),
|
||||
ctx->getDelayNS(delay));
|
||||
}
|
||||
|
||||
log_break();
|
||||
}
|
||||
|
||||
for (auto &eclock : empty_clocks) {
|
||||
if (eclock != ctx->id("$async$"))
|
||||
log_info("Clock '%s' has no interior paths\n", eclock.c_str(ctx));
|
||||
}
|
||||
log_break();
|
||||
|
||||
int start_field_width = 0, end_field_width = 0;
|
||||
for (auto &report : xclock_reports) {
|
||||
start_field_width = std::max((int)format_event(report.clock_pair.start).length(), start_field_width);
|
||||
end_field_width = std::max((int)format_event(report.clock_pair.end).length(), end_field_width);
|
||||
}
|
||||
|
||||
for (auto &report : xclock_reports) {
|
||||
const ClockEvent &a = report.clock_pair.start;
|
||||
const ClockEvent &b = report.clock_pair.end;
|
||||
delay_t path_delay = 0;
|
||||
for (const auto &segment : report.segments) {
|
||||
path_delay += segment.delay;
|
||||
}
|
||||
auto ev_a = format_event(a, start_field_width), ev_b = format_event(b, end_field_width);
|
||||
log_info("Max delay %s -> %s: %0.02f ns\n", ev_a.c_str(), ev_b.c_str(), ctx->getDelayNS(path_delay));
|
||||
}
|
||||
log_break();
|
||||
}
|
||||
}
|
||||
|
||||
@ -1317,6 +1095,7 @@ domain_id_t TimingAnalyser::domain_id(IdString cell, IdString clock_port, ClockE
|
||||
{
|
||||
return domain_id(ctx->cells.at(cell)->ports.at(clock_port).net, edge);
|
||||
}
|
||||
|
||||
domain_id_t TimingAnalyser::domain_id(const NetInfo *net, ClockEdge edge)
|
||||
{
|
||||
NPNR_ASSERT(net != nullptr);
|
||||
@ -1327,6 +1106,7 @@ domain_id_t TimingAnalyser::domain_id(const NetInfo *net, ClockEdge edge)
|
||||
}
|
||||
return inserted.first->second;
|
||||
}
|
||||
|
||||
domain_id_t TimingAnalyser::domain_pair_id(domain_id_t launch, domain_id_t capture)
|
||||
{
|
||||
ClockDomainPairKey key{launch, capture};
|
||||
|
||||
@ -74,9 +74,8 @@ struct TimingAnalyser
|
||||
{
|
||||
public:
|
||||
TimingAnalyser(Context *ctx);
|
||||
void setup();
|
||||
void run(bool update_route_delays = true);
|
||||
void print_report();
|
||||
void setup(bool update_net_timings = false, bool update_histogram = false, bool update_crit_paths = false, bool update_route_delays = true);
|
||||
void run(bool update_net_timings = false, bool update_histogram = false, bool update_crit_paths = false, bool update_route_delays = true);
|
||||
|
||||
// This is used when routers etc are not actually binding detailed routing (due to congestion or an abstracted
|
||||
// model), but want to re-run STA with their own calculated delays
|
||||
@ -115,17 +114,20 @@ struct TimingAnalyser
|
||||
void compute_slack();
|
||||
void compute_criticality();
|
||||
|
||||
dict<domain_id_t, delay_t> max_delay_by_domain();
|
||||
void build_detailed_net_timing_report();
|
||||
// Build up CriticalPathData
|
||||
CriticalPath build_critical_path_report(domain_id_t domain_pair, CellPortKey endpoint);
|
||||
void build_crit_path_reports();
|
||||
void build_slack_histogram_report();
|
||||
|
||||
|
||||
dict<domain_id_t, delay_t> max_delay_by_domain_pairs();
|
||||
|
||||
// get the N most failing endpoints for a given domain pair
|
||||
std::vector<CellPortKey> get_failing_eps(domain_id_t domain_pair, int count);
|
||||
std::vector<CellPortKey> get_worst_eps(domain_id_t domain_pair, int count);
|
||||
// print the critical path for an endpoint and domain pair
|
||||
void print_critical_path(CellPortKey endpoint, domain_id_t domain_pair);
|
||||
|
||||
// Build up CriticalPathData
|
||||
// Build critical path report
|
||||
CriticalPath build_critical_path_report(domain_id_t domain_pair, CellPortKey endpoint);
|
||||
|
||||
const DelayPair init_delay{std::numeric_limits<delay_t>::max(), std::numeric_limits<delay_t>::lowest()};
|
||||
|
||||
// Set arrival/required times if more/less than the current value
|
||||
|
||||
@ -26,6 +26,8 @@
|
||||
#include "log.h"
|
||||
#include "timing.h"
|
||||
#include "util.h"
|
||||
#include <fstream>
|
||||
#include <iostream>
|
||||
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
@ -606,6 +608,10 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
|
||||
DelayFrequency slack_histogram;
|
||||
DetailedNetTimings detailed_net_timings;
|
||||
|
||||
print_path = true;
|
||||
update_results = true;
|
||||
print_histogram = true;
|
||||
|
||||
Timing timing(ctx, true /* net_delays */, false /* update */, (print_path || print_fmax) ? &crit_paths : nullptr,
|
||||
print_histogram ? &slack_histogram : nullptr,
|
||||
(update_results && ctx->detailed_timing_report) ? &detailed_net_timings : nullptr);
|
||||
@ -613,12 +619,18 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
|
||||
|
||||
// Use TimingAnalyser to determine clock-to-clock relations
|
||||
TimingAnalyser timingAnalyser(ctx);
|
||||
timingAnalyser.setup();
|
||||
timingAnalyser.setup(true, true, true, true);
|
||||
|
||||
log("start timingAnalyser.print_report();\n\n");
|
||||
timingAnalyser.print_report();
|
||||
// timingAnalyser.print_report();
|
||||
log("end timingAnalyser.print_report();\n\n");
|
||||
|
||||
std::string filename = "timingAnalyser.json";
|
||||
std::ofstream f(filename);
|
||||
if (!f)
|
||||
log_error("Failed to open report file '%s' for writing.\n", filename.c_str());
|
||||
ctx->writeReport(f);
|
||||
|
||||
bool report_critical_paths = print_path || print_fmax || update_results;
|
||||
|
||||
dict<IdString, CriticalPath> clock_reports;
|
||||
@ -633,6 +645,7 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
|
||||
const ClockEvent &b = path.first.end;
|
||||
empty_clocks.insert(a.clock);
|
||||
empty_clocks.insert(b.clock);
|
||||
log_info("timing_old: clock pair: %s -> %s\n", a.clock.c_str(ctx), b.clock.c_str(ctx));
|
||||
}
|
||||
for (auto path : crit_paths) {
|
||||
const ClockEvent &a = path.first.start;
|
||||
@ -1023,6 +1036,12 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
|
||||
|
||||
results.detailed_net_timings = std::move(detailed_net_timings);
|
||||
}
|
||||
|
||||
std::string filename2 = "timing_old.json";
|
||||
std::ofstream f2(filename2);
|
||||
if (!f)
|
||||
log_error("Failed to open report file '%s' for writing.\n", filename.c_str());
|
||||
ctx->writeReport(f2);
|
||||
}
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
|
||||
Loading…
Reference in New Issue
Block a user