Add examples invoking FPGA interchange nextpnr.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

fpga_interchange/examples/archcheck/Makefile

@@ -0,0 +1,16 @@
+NEXTPNR_PATH := $(shell echo ~/cat_x/nextpnr)
+NEXTPNR_BIN := $(NEXTPNR_PATH)/build/nextpnr-fpga_interchange
+BBA_PATH := $(NEXTPNR_PATH)/build/test.bin
+
+PACKAGE := csg324
+
+.PHONY:
+
+check:
+	$(NEXTPNR_BIN) \
+		--chipdb $(BBA_PATH) \
+		--package $(PACKAGE) \
+		--test
+	$(NEXTPNR_BIN) \
+		--chipdb $(BBA_PATH) \
+		--run $(NEXTPNR_PATH)/python/check_arch_api.py

fpga_interchange/examples/archcheck/test_data.yaml

@@ -0,0 +1,7 @@
+pip_test:
+    - src_wire: CLBLM_R_X11Y93/CLBLM_L_D3
+      dst_wire: SLICE_X15Y93.SLICEL/D3
+bel_pin_test:
+    - bel: SLICE_X15Y93.SLICEL/D6LUT
+      pin: A3
+      wire: SLICE_X15Y93.SLICEL/D3

fpga_interchange/examples/lut/Makefile

@@ -0,0 +1,8 @@
+DESIGN := lut
+DESIGN_TOP := top
+PACKAGE := csg324
+
+include ../template.mk
+
+build/lut.json: lut.v | build
+	yosys -c run.tcl

fpga_interchange/examples/lut/lut.v

@@ -0,0 +1,5 @@
+module top(input i0, input i1, output o);
+
+assign o = i0 | i1;
+
+endmodule

fpga_interchange/examples/lut/lut.xdc

@@ -0,0 +1,5 @@
+set_property PACKAGE_PIN N16 [get_ports i0]
+set_property PACKAGE_PIN N15 [get_ports i1]
+set_property PACKAGE_PIN M17 [get_ports o]
+
+#set_property IOSTANDARD LVCMOS33 [get_ports]

fpga_interchange/examples/lut/run.tcl

@@ -0,0 +1,14 @@
+yosys -import
+
+read_verilog lut.v
+
+synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
+
+# opt_expr -undriven makes sure all nets are driven, if only by the $undef
+# net.
+opt_expr -undriven
+opt_clean
+
+setundef -zero -params
+
+write_json build/lut.json

fpga_interchange/examples/template.mk

@@ -0,0 +1,68 @@
+NEXTPNR_PATH := $(shell echo ~/cat_x/nextpnr)
+NEXTPNR_BIN := $(NEXTPNR_PATH)/build/nextpnr-fpga_interchange
+BBA_PATH := $(NEXTPNR_PATH)/build/test.bin
+
+RAPIDWRIGHT_PATH := $(shell echo ~/cat_x/RapidWright)
+
+INTERCHANGE_PATH := $(NEXTPNR_PATH)/3rdparty/fpga-interchange-schema/interchange
+
+DEVICE := $(shell echo ~/cat_x/python-fpga-interchange/xc7a35tcpg236-1_constraints_luts.device)
+
+.DELETE_ON_ERROR:
+.PHONY: all debug clean
+
+all: build/$(DESIGN).dcp
+
+build:
+	mkdir build
+
+build/$(DESIGN).netlist: build/$(DESIGN).json
+	/usr/bin/time -v python3 -mfpga_interchange.yosys_json \
+		--schema_dir $(INTERCHANGE_PATH) \
+		--device $(DEVICE) \
+		--top $(DESIGN_TOP) \
+		build/$(DESIGN).json \
+		build/$(DESIGN).netlist
+
+build/$(DESIGN)_netlist.yaml: build/$(DESIGN).netlist
+	/usr/bin/time -v python3 -mfpga_interchange.convert \
+		--schema_dir $(INTERCHANGE_PATH) \
+		--schema logical \
+		--input_format capnp \
+		--output_format yaml \
+		build/$(DESIGN).netlist \
+		build/$(DESIGN)_netlist.yaml
+
+build/$(DESIGN).phys: build/$(DESIGN).netlist
+	$(NEXTPNR_BIN) \
+		--chipdb $(BBA_PATH) \
+		--xdc $(DESIGN).xdc \
+		--netlist build/$(DESIGN).netlist \
+		--phys build/$(DESIGN).phys \
+		--package $(PACKAGE)
+
+build/$(DESIGN)_phys.yaml: build/$(DESIGN).phys
+	/usr/bin/time -v python3 -mfpga_interchange.convert \
+		--schema_dir $(INTERCHANGE_PATH) \
+		--schema physical \
+		--input_format capnp \
+		--output_format yaml \
+		build/$(DESIGN).phys \
+		build/$(DESIGN)_phys.yaml
+
+debug: build/$(DESIGN).netlist
+	gdb --args $(NEXTPNR_BIN) \
+		--chipdb $(BBA_PATH) \
+		--xdc $(DESIGN).xdc \
+		--netlist build/$(DESIGN).netlist \
+		--phys build/$(DESIGN).phys \
+		--package $(PACKAGE)
+
+build/$(DESIGN).dcp: build/$(DESIGN).netlist build/$(DESIGN).phys $(DESIGN).xdc
+	RAPIDWRIGHT_PATH=$(RAPIDWRIGHT_PATH) \
+		$(RAPIDWRIGHT_PATH)/scripts/invoke_rapidwright.sh \
+		com.xilinx.rapidwright.interchange.PhysicalNetlistToDcp \
+		build/$(DESIGN).netlist build/$(DESIGN).phys $(DESIGN).xdc build/$(DESIGN).dcp
+
+clean::
+	rm -rf build

fpga_interchange/examples/wire/Makefile

@@ -0,0 +1,8 @@
+DESIGN := wire
+DESIGN_TOP := top
+PACKAGE := csg324
+
+include ../template.mk
+
+build/wire.json: wire.v | build
+	yosys -c run.tcl

fpga_interchange/examples/wire/run.tcl

@@ -0,0 +1,14 @@
+yosys -import
+
+read_verilog wire.v
+
+synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
+
+# opt_expr -undriven makes sure all nets are driven, if only by the $undef
+# net.
+opt_expr -undriven
+opt_clean
+
+setundef -zero -params
+
+write_json build/wire.json

fpga_interchange/examples/wire/wire.v

@@ -0,0 +1,5 @@
+module top(input i, output o);
+
+assign o = i;
+
+endmodule

fpga_interchange/examples/wire/wire.xdc

@@ -0,0 +1,2 @@
+set_property PACKAGE_PIN N16 [get_ports i]
+set_property PACKAGE_PIN N15 [get_ports o]