diff --git a/common/router1.cc b/common/router1.cc
index 86fb1a44..767e10fd 100644
--- a/common/router1.cc
+++ b/common/router1.cc
@@ -22,6 +22,7 @@
 
 #include "log.h"
 #include "router1.h"
+#include "timing.h"
 
 namespace {
 
@@ -730,8 +731,25 @@ bool router1(Context *ctx)
 
             std::unordered_set<IdString> normalRouteNets, ripupQueue;
 
-            if (ctx->verbose || iterCnt == 1)
-                log_info("routing queue contains %d jobs.\n", int(jobQueue.size()));
+            if (iterCnt == 1) {
+                if (ctx->verbose)
+                    log_info("routing queue contains %d jobs.\n", int(jobQueue.size()));
+            } else {
+                static auto actual_delay = [](Context *ctx, WireId src, WireId dst) {
+                    delay_t total_delay = ctx->getWireDelay(dst).maxDelay();
+                    WireId last_wire = dst;
+                    for (auto pip : ctx->getPipsDownhill(dst)) {
+                        total_delay += ctx->getPipDelay(pip).maxDelay();
+                        WireId next_wire = ctx->getPipDstWire(pip);
+                        total_delay += ctx->getWireDelay(next_wire).maxDelay();
+                    }
+                    NPNR_ASSERT(last_wire != WireId());
+                    if (last_wire != src)
+                        total_delay += ctx->estimateDelay(src, last_wire);
+                    return total_delay;
+                };
+                update_budget(ctx, actual_delay);
+            }
 
             bool printNets = ctx->verbose && (jobQueue.size() < 10);
 
diff --git a/common/timing.cc b/common/timing.cc
index 9723550b..0e84dded 100644
--- a/common/timing.cc
+++ b/common/timing.cc
@@ -164,7 +164,7 @@ static delay_t follow_net_update(Context *ctx, NetInfo *net, int path_length, de
     return net_budget;
 }
 
-void update_budget(Context *ctx)
+void update_budget(Context *ctx, std::function<delay_t(Context*,WireId,WireId)> delay_fn)
 {
     delays_t delays;
     updates_t updates;
@@ -191,7 +191,7 @@ void update_budget(Context *ctx)
             if (load_cell->bel == BelId())
                 continue;
             WireId user_wire = ctx->getWireBelPin(load_cell->bel, ctx->portPinFromId(load.port));
-            delay_t raw_wl = ctx->estimateDelay(drv_wire, user_wire);
+            delay_t raw_wl = delay_fn(ctx, drv_wire, user_wire);
             delays.emplace(&load_cell->ports.at(load.port), raw_wl);
         }
     }
diff --git a/common/timing.h b/common/timing.h
index b5574392..8c098963 100644
--- a/common/timing.h
+++ b/common/timing.h
@@ -27,7 +27,7 @@ NEXTPNR_NAMESPACE_BEGIN
 // Assign "budget" values for all user ports in the design
 void assign_budget(Context *ctx);
 
-void update_budget(Context *ctx);
+void update_budget(Context *ctx, std::function<delay_t(Context*,WireId,WireId)> delay_fn=&Context::estimateDelay);
 
 NEXTPNR_NAMESPACE_END